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giz alpha1 release
[picodrive.git]
/
Pico
/
cd
/
Pico.s
diff --git
a/Pico/cd/Pico.s
b/Pico/cd/Pico.s
index
24e4d1c
..
b1f554c
100644
(file)
--- a/
Pico/cd/Pico.s
+++ b/
Pico/cd/Pico.s
@@
-36,8
+36,8
@@
SekRunPS:
ldr lr, =PicoCpuS68k
ldr r2, =CycloneEnd_M68k
ldr r3, =CycloneEnd_S68k
ldr lr, =PicoCpuS68k
ldr r2, =CycloneEnd_M68k
ldr r3, =CycloneEnd_S68k
- str r2, [r7,#0x
54
]
- str r3, [lr,#0x
54
]
+ str r2, [r7,#0x
98
]
+ str r3, [lr,#0x
98
]
@ update aims
ldr r8, =SekCycleAim
@ update aims
ldr r8, =SekCycleAim
@@
-83,8
+83,9
@@
schedule_s68k:
ldr r9, [r9]
sub r0, r9, r8
ldr r9, [r9]
sub r0, r9, r8
- add r3, r3, r3, asr #1
- add r3, r3, r3, asr #3 @ cycn_s68k = (cycn + cycn/2 + cycn/8)
+ mov r2, r3
+ add r3, r3, r2, asr #1
+ add r3, r3, r2, asr #3 @ cycn_s68k = (cycn + cycn/2 + cycn/8)
subs r5, r0, r3, asr #16
ble schedule_m68k @ s68k has not enough cycles
subs r5, r0, r3, asr #16
ble schedule_m68k @ s68k has not enough cycles
@@
-131,15
+132,14
@@
SekRunPS_end:
ldr r7, =PicoCpu
ldr lr, =PicoCpuS68k
mov r0, #0
ldr r7, =PicoCpu
ldr lr, =PicoCpuS68k
mov r0, #0
- str r0, [r7,#0x
54
] @ remove CycloneEnd handler
- str r0, [lr,#0x
54
]
+ str r0, [r7,#0x
98
] @ remove CycloneEnd handler
+ str r0, [lr,#0x
98
]
@ return
add sp, sp, #2*4
ldmfd sp!, {r4-r11,pc}
@ return
add sp, sp, #2*4
ldmfd sp!, {r4-r11,pc}
-
CycloneRunLocal:
;@ r0-3 = Temporary registers
ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base
CycloneRunLocal:
;@ r0-3 = Temporary registers
ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base
@@
-148,32
+148,33
@@
CycloneRunLocal:
;@ r7 = Pointer to Cpu Context
;@ r8 = Current Opcode
ldrb r9,[r7,#0x46] ;@ r9 = Flags (NZCV)
;@ r7 = Pointer to Cpu Context
;@ r8 = Current Opcode
ldrb r9,[r7,#0x46] ;@ r9 = Flags (NZCV)
- ldr r
0,[r7,#0x44]
-
mov r9,r9,lsl #28
;@ r9 = Flags 0xf0000000, cpsr format
+ ldr r
1,[r7,#0x44] ;@ get SR high and IRQ level
+
orr r9,r9,r9,lsl #28
;@ r9 = Flags 0xf0000000, cpsr format
;@ r10 = Source value / Memory Base
;@ CheckInterrupt:
;@ r10 = Source value / Memory Base
;@ CheckInterrupt:
- movs r0,r
0
,lsr #24 ;@ Get IRQ level
+ movs r0,r
1
,lsr #24 ;@ Get IRQ level
beq NoIntsLocal
cmp r0,#6 ;@ irq>6 ?
beq NoIntsLocal
cmp r0,#6 ;@ irq>6 ?
- ldrleb r1,[r7,#0x44] ;@ Get SR high: T_S__III
andle r1,r1,#7 ;@ Get interrupt mask
cmple r0,r1 ;@ irq<=6: Is irq<=mask ?
andle r1,r1,#7 ;@ Get interrupt mask
cmple r0,r1 ;@ irq<=6: Is irq<=mask ?
- blgt CycloneDoInterrupt
-;@ Check if interrupt used up all the cycles:
- subs r5,r5,#0
- ldrlt r1,[r7,#0x54]
- bxlt r1 ;@ jump to alternative CycloneEnd
+ bgt CycloneDoInterrupt
NoIntsLocal:
NoIntsLocal:
-;@ Check if our processor is in stopped state and jump to opcode handler if not
- ldr r0,[r7,#0x58]
+;@ Check if our processor is in special state
+;@ and jump to opcode handler if not
+ ldr r0,[r7,#0x58] ;@ state_flags
ldrh r8,[r4],#2 ;@ Fetch first opcode
ldrh r8,[r4],#2 ;@ Fetch first opcode
- tst r0,r0 ;@ stopped?
+ tst r0,#0x03 ;@ special state?
+ andeq r9,r9,#0xf0000000
ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler
ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler
- @ stopped
- ldr r1,[r7,#0x54]
+CycloneSpecial2:
+ tst r0,#2 ;@ tracing?
+ bne CycloneDoTrace
+;@ stopped or halted
+ sub r4,r4,#2
+ ldr r1,[r7,#0x98]
mov r5,#0
bx r1
mov r5,#0
bx r1