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[picodrive.git]
/
cpu
/
Cyclone
/
OpLogic.cpp
diff --git
a/cpu/Cyclone/OpLogic.cpp
b/cpu/Cyclone/OpLogic.cpp
index
4a795e4
..
b6eb075
100644
(file)
--- a/
cpu/Cyclone/OpLogic.cpp
+++ b/
cpu/Cyclone/OpLogic.cpp
@@
-27,7
+27,7
@@
int OpBtstReg(int op)
use&=~0x0e00; // Use same handler for all registers
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
use&=~0x0e00; // Use same handler for all registers
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
- OpStart(op);
\r
+ OpStart(op
,tea
);
\r
\r
if(type==1||type==3) {
\r
Cycles=8;
\r
\r
if(type==1||type==3) {
\r
Cycles=8;
\r
@@
-88,7
+88,7
@@
int OpBtstImm(int op)
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
- OpStart(op);
\r
+ OpStart(op
,sea|tea
);
\r
\r
ot(" mov r10,#1\n");
\r
ot("\n");
\r
\r
ot(" mov r10,#1\n");
\r
ot("\n");
\r
@@
-145,10
+145,10
@@
int OpNeg(int op)
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
- OpStart(op); Cycles=size<2?4:6;
\r
+ OpStart(op
,ea
); Cycles=size<2?4:6;
\r
if(ea >= 0x10) {
\r
Cycles*=2;
\r
if(ea >= 0x10) {
\r
Cycles*=2;
\r
-#if
def
CYCLONE_FOR_GENESIS
\r
+#if CYCLONE_FOR_GENESIS
\r
// This is same as in Starscream core, CLR uses only 6 cycles for memory EAs.
\r
// May be this is similar case as with TAS opcode, but this time the dummy
\r
// read is ignored somehow? Without this hack Fatal Rewind hangs even in Gens.
\r
// This is same as in Starscream core, CLR uses only 6 cycles for memory EAs.
\r
// May be this is similar case as with TAS opcode, but this time the dummy
\r
// read is ignored somehow? Without this hack Fatal Rewind hangs even in Gens.
\r
@@
-170,10
+170,10
@@
int OpNeg(int op)
ot(" orr r3,r9,#0xb0000000 ;@ for old Z\n");
\r
OpGetFlags(1,1,0);
\r
if(size!=2) {
\r
ot(" orr r3,r9,#0xb0000000 ;@ for old Z\n");
\r
OpGetFlags(1,1,0);
\r
if(size!=2) {
\r
-
ot(" movs r1,r1,asr #%i\n",size?16:24);
\r
+ ot(" movs r1,r1,asr #%i\n",size?16:24);
\r
ot(" orreq r9,r9,#0x40000000 ;@ possily missed Z\n");
\r
ot(" orreq r9,r9,#0x40000000 ;@ possily missed Z\n");
\r
-
}
\r
-
ot(" andeq r9,r9,r3 ;@ fix Z\n");
\r
+ }
\r
+ ot(" andeq r9,r9,r3 ;@ fix Z\n");
\r
ot("\n");
\r
}
\r
\r
ot("\n");
\r
}
\r
\r
@@
-254,7
+254,7
@@
int OpTst(int op)
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
- OpStart(op); Cycles=4;
\r
+ OpStart(op
,sea
); Cycles=4;
\r
\r
EaCalc ( 0,0x003f,sea,size,1);
\r
EaRead ( 0, 0,sea,size,0x003f,1);
\r
\r
EaCalc ( 0,0x003f,sea,size,1);
\r
EaRead ( 0, 0,sea,size,0x003f,1);
\r
@@
-322,7
+322,7
@@
int OpSet(int op)
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
- OpStart(op); Cycles=8;
\r
+ OpStart(op
,ea
); Cycles=8;
\r
if (ea<8) Cycles=4;
\r
\r
ot(" mov r1,#0\n");
\r
if (ea<8) Cycles=4;
\r
\r
ot(" mov r1,#0\n");
\r
@@
-429,9
+429,9
@@
static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
if(count == 1) {
\r
if(dir==0) {
\r
if(size!=2) {
\r
if(count == 1) {
\r
if(dir==0) {
\r
if(size!=2) {
\r
-
ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);
\r
-
ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));
\r
-
}
\r
+ ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);
\r
+ ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));
\r
+ }
\r
GetXBit(0);
\r
ot(" movs r0,r0,rrx\n");
\r
OpGetFlags(0,1);
\r
GetXBit(0);
\r
ot(" movs r0,r0,rrx\n");
\r
OpGetFlags(0,1);
\r
@@
-619,7
+619,7
@@
int OpAsrEa(int op)
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
- OpStart(op); Cycles=6; // EmitAsr() will add 2
\r
+ OpStart(op
,ea
); Cycles=6; // EmitAsr() will add 2
\r
\r
EaCalc (10,0x003f,ea,size,1);
\r
EaRead (10, 0,ea,size,0x003f,1);
\r
\r
EaCalc (10,0x003f,ea,size,1);
\r
EaRead (10, 0,ea,size,0x003f,1);
\r
@@
-632,7
+632,7
@@
int OpAsrEa(int op)
return 0;
\r
}
\r
\r
return 0;
\r
}
\r
\r
-int OpTas(int op)
\r
+int OpTas(int op
, int gen_special
)
\r
{
\r
int ea=0;
\r
int use=0;
\r
{
\r
int ea=0;
\r
int use=0;
\r
@@
-645,7
+645,11
@@
int OpTas(int op)
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
use=OpBase(op);
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
\r
\r
- OpStart(op); Cycles=4;
\r
+ if (!gen_special) OpStart(op,ea);
\r
+ else
\r
+ ot("Op%.4x_%s\n", op, ms?"":":");
\r
+
\r
+ Cycles=4;
\r
if(ea>=8) Cycles+=10;
\r
\r
EaCalc (10,0x003f,ea,0,1);
\r
if(ea>=8) Cycles+=10;
\r
\r
EaCalc (10,0x003f,ea,0,1);
\r
@@
-657,7
+661,7
@@
int OpTas(int op)
\r
#if CYCLONE_FOR_GENESIS
\r
// the original Sega hardware ignores write-back phase (to memory only)
\r
\r
#if CYCLONE_FOR_GENESIS
\r
// the original Sega hardware ignores write-back phase (to memory only)
\r
- if (ea < 0x10) {
\r
+ if (ea < 0x10
|| gen_special
) {
\r
#endif
\r
ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");
\r
\r
#endif
\r
ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");
\r
\r
@@
-667,6
+671,13
@@
int OpTas(int op)
#endif
\r
\r
OpEnd();
\r
#endif
\r
\r
OpEnd();
\r
+
\r
+#if (CYCLONE_FOR_GENESIS == 2)
\r
+ if (!gen_special && ea >= 0x10) {
\r
+ OpTas(op, 1);
\r
+ }
\r
+#endif
\r
+
\r
return 0;
\r
}
\r
\r
return 0;
\r
}
\r
\r