-/*\r
- * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r
- * counter in ARM registers instead of the context for performance reasons. If you for\r
- * any reason need to access them in your memory handlers, enable the options below,\r
- * otherwise disable them to improve performance.\r
- *\r
- * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
- * when memhandler was called (opcode address + 2-10 bytes).\r
- * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
- * opcode address + 2.\r
- * Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
- * subtract .membase to get M68k PC value.\r
- *\r
- * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
- * increment the PC before fetching the next instruction and continue executing\r
- * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.\r
- *\r
- * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable\r
- * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle\r
- * count and this will screw timing (if not cause a deadlock).\r
- */\r
-#define MEMHANDLERS_NEED_PC 1\r