+ rcache_free_tmp(tmp_); \
+}
+
+#define emith_write_sr(sr, srcr) { \
+ emith_lsr(sr, sr, 10); \
+ emith_or_r_r_r_lsl(sr, sr, srcr, 22); \
+ emith_ror(sr, sr, 22); \
+}
+
+#define emith_carry_to_t(srr, is_sub) { \
+ if (is_sub) { /* has inverted C on ARM */ \
+ emith_or_r_imm_c(A_COND_CC, srr, 1); \
+ emith_bic_r_imm_c(A_COND_CS, srr, 1); \
+ } else { \
+ emith_or_r_imm_c(A_COND_CS, srr, 1); \
+ emith_bic_r_imm_c(A_COND_CC, srr, 1); \
+ } \
+}
+
+#define emith_tpop_carry(sr, is_sub) { \
+ if (is_sub) \
+ emith_eor_r_imm(sr, 1); \
+ emith_lsrf(sr, sr, 1); \
+}
+
+#define emith_tpush_carry(sr, is_sub) { \
+ emith_adc_r_r(sr, sr); \
+ if (is_sub) \
+ emith_eor_r_imm(sr, 1); \
+}
+
+/*
+ * if Q
+ * t = carry(Rn += Rm)
+ * else
+ * t = carry(Rn -= Rm)
+ * T ^= t
+ */
+#define emith_sh2_div1_step(rn, rm, sr) { \
+ void *jmp0, *jmp1; \
+ emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
+ JMP_POS(jmp0); /* beq do_sub */ \
+ emith_addf_r_r(rn, rm); \
+ emith_eor_r_imm_c(A_COND_CS, sr, T); \
+ JMP_POS(jmp1); /* b done */ \
+ JMP_EMIT(A_COND_EQ, jmp0); /* do_sub: */ \
+ emith_subf_r_r(rn, rm); \
+ emith_eor_r_imm_c(A_COND_CC, sr, T); \
+ JMP_EMIT(A_COND_AL, jmp1); /* done: */ \