+ return ret;
+}
+
+static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
+{
+ return rcache_get_reg_(r, mode, 1);
+}
+
+static int rcache_get_tmp(void)
+{
+ temp_reg_t *tr;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
+ if (reg_temp[i].type == HR_FREE) {
+ tr = ®_temp[i];
+ goto do_alloc;
+ }
+
+ tr = rcache_evict();
+
+do_alloc:
+ tr->type = HR_TEMP;
+ return tr->hreg;
+}
+
+static int rcache_get_arg_id(int arg)
+{
+ int i, r = 0;
+ host_arg2reg(r, arg);
+
+ for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
+ if (reg_temp[i].hreg == r)
+ break;
+
+ if (i == ARRAY_SIZE(reg_temp)) // can't happen
+ exit(1);
+
+ if (reg_temp[i].type == HR_CACHED) {
+ // writeback
+ if (reg_temp[i].flags & HRF_DIRTY)
+ emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
+ gconst_check_evict(reg_temp[i].greg);
+ }
+ else if (reg_temp[i].type == HR_TEMP) {
+ printf("arg %d reg %d already used, aborting\n", arg, r);
+ exit(1);
+ }
+
+ reg_temp[i].type = HR_FREE;
+ reg_temp[i].flags = 0;
+
+ return i;
+}
+
+// get a reg to be used as function arg
+static int rcache_get_tmp_arg(int arg)
+{
+ int id = rcache_get_arg_id(arg);
+ reg_temp[id].type = HR_TEMP;
+
+ return reg_temp[id].hreg;
+}
+
+// same but caches a reg. RC_GR_READ only.
+static int rcache_get_reg_arg(int arg, sh2_reg_e r)
+{
+ int i, srcr, dstr, dstid;
+ int dirty = 0, src_dirty = 0;
+
+ dstid = rcache_get_arg_id(arg);
+ dstr = reg_temp[dstid].hreg;
+
+ // maybe already statically mapped?
+ srcr = get_reg_static(r, RC_GR_READ);
+ if (srcr != -1)
+ goto do_cache;
+
+ // maybe already cached?
+ for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
+ if ((reg_temp[i].type == HR_CACHED) &&
+ reg_temp[i].greg == r)
+ {
+ srcr = reg_temp[i].hreg;
+ if (reg_temp[i].flags & HRF_DIRTY)
+ src_dirty = 1;
+ goto do_cache;
+ }
+ }
+
+ // must read
+ srcr = dstr;
+ if (gconst_check(r)) {
+ if (gconst_try_read(srcr, r))
+ dirty = 1;
+ }
+ else
+ emith_ctx_read(srcr, r * 4);
+
+do_cache:
+ if (dstr != srcr)
+ emith_move_r_r(dstr, srcr);
+#if 1
+ else
+ dirty |= src_dirty;
+
+ if (dirty)
+ // must clean, callers might want to modify the arg before call
+ emith_ctx_write(dstr, r * 4);
+#else
+ if (dirty)
+ reg_temp[dstid].flags |= HRF_DIRTY;
+#endif
+
+ reg_temp[dstid].stamp = ++rcache_counter;
+ reg_temp[dstid].type = HR_CACHED;
+ reg_temp[dstid].greg = r;
+ reg_temp[dstid].flags |= HRF_LOCKED;
+ return dstr;
+}
+
+static void rcache_free_tmp(int hr)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
+ if (reg_temp[i].hreg == hr)
+ break;
+
+ if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
+ printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
+ return;
+ }
+
+ reg_temp[i].type = HR_FREE;
+ reg_temp[i].flags = 0;
+}
+
+static void rcache_unlock(int hr)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
+ if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
+ reg_temp[i].flags &= ~HRF_LOCKED;
+}
+
+static void rcache_unlock_all(void)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
+ reg_temp[i].flags &= ~HRF_LOCKED;
+}
+
+static inline u32 rcache_used_hreg_mask(void)
+{
+ u32 mask = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
+ if (reg_temp[i].type != HR_FREE)
+ mask |= 1 << reg_temp[i].hreg;
+
+ return mask;
+}
+
+static void rcache_clean(void)
+{
+ int i;
+ gconst_clean();
+
+ for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
+ if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
+ // writeback
+ emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
+ reg_temp[i].flags &= ~HRF_DIRTY;
+ }
+}
+
+static void rcache_invalidate(void)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
+ reg_temp[i].type = HR_FREE;
+ reg_temp[i].flags = 0;
+ }
+ rcache_counter = 0;
+
+ gconst_invalidate();
+}
+
+static void rcache_flush(void)
+{
+ rcache_clean();
+ rcache_invalidate();
+}
+
+// ---------------------------------------------------------------
+
+static int emit_get_rbase_and_offs(u32 a, u32 *offs)
+{
+ u32 mask = 0;
+ int poffs;
+ int hr;
+
+ poffs = dr_ctx_get_mem_ptr(a, &mask);
+ if (poffs == -1)
+ return -1;
+
+ // XXX: could use some related reg
+ hr = rcache_get_tmp();
+ emith_ctx_read(hr, poffs);
+ emith_add_r_imm(hr, a & mask & ~0xff);
+ *offs = a & 0xff; // XXX: ARM oriented..
+ return hr;
+}
+
+static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
+{
+#if PROPAGATE_CONSTANTS
+ gconst_new(dst, imm);
+#else
+ int hr = rcache_get_reg(dst, RC_GR_WRITE);
+ emith_move_r_imm(hr, imm);
+#endif
+}
+
+static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
+{
+ int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
+ int hr_s = rcache_get_reg(src, RC_GR_READ);
+
+ emith_move_r_r(hr_d, hr_s);
+}
+
+// T must be clear, and comparison done just before this
+static void emit_or_t_if_eq(int srr)
+{
+ EMITH_SJMP_START(DCOND_NE);
+ emith_or_r_imm_c(DCOND_EQ, srr, T);
+ EMITH_SJMP_END(DCOND_NE);
+}
+
+// arguments must be ready
+// reg cache must be clean before call
+static int emit_memhandler_read_(int size, int ram_check)
+{
+ int arg1;
+#if 0
+ int arg0;
+ host_arg2reg(arg0, 0);
+#endif
+
+ rcache_clean();
+
+ // must writeback cycles for poll detection stuff
+ // FIXME: rm
+ if (reg_map_g2h[SHR_SR] != -1)
+ emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
+
+ arg1 = rcache_get_tmp_arg(1);
+ emith_move_r_r(arg1, CONTEXT_REG);
+
+#if 0 // can't do this because of unmapped reads
+ // ndef PDB_NET
+ if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
+ int tmp = rcache_get_tmp();
+ emith_and_r_r_imm(tmp, arg0, 0xfb000000);
+ emith_cmp_r_imm(tmp, 0x02000000);
+ switch (size) {
+ case 0: // 8
+ EMITH_SJMP3_START(DCOND_NE);
+ emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
+ emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
+ EMITH_SJMP3_MID(DCOND_NE);
+ emith_call_cond(DCOND_NE, sh2_drc_read8);
+ EMITH_SJMP3_END();
+ break;
+ case 1: // 16
+ EMITH_SJMP3_START(DCOND_NE);
+ emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
+ EMITH_SJMP3_MID(DCOND_NE);
+ emith_call_cond(DCOND_NE, sh2_drc_read16);
+ EMITH_SJMP3_END();
+ break;
+ case 2: // 32
+ EMITH_SJMP3_START(DCOND_NE);
+ emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
+ emith_ror_c(DCOND_EQ, arg0, arg0, 16);
+ EMITH_SJMP3_MID(DCOND_NE);
+ emith_call_cond(DCOND_NE, sh2_drc_read32);
+ EMITH_SJMP3_END();
+ break;
+ }
+ }
+ else
+#endif
+ {
+ switch (size) {
+ case 0: // 8
+ emith_call(sh2_drc_read8);
+ break;
+ case 1: // 16
+ emith_call(sh2_drc_read16);
+ break;
+ case 2: // 32
+ emith_call(sh2_drc_read32);
+ break;
+ }
+ }
+ rcache_invalidate();
+
+ if (reg_map_g2h[SHR_SR] != -1)
+ emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
+
+ // assuming arg0 and retval reg matches
+ return rcache_get_tmp_arg(0);
+}
+
+static int emit_memhandler_read(int size)
+{
+ return emit_memhandler_read_(size, 1);
+}
+
+static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
+{
+ int hr, hr2, ram_check = 1;
+ u32 val, offs2;
+
+ if (gconst_get(rs, &val)) {
+ hr = emit_get_rbase_and_offs(val + offs, &offs2);
+ if (hr != -1) {
+ hr2 = rcache_get_reg(rd, RC_GR_WRITE);
+ switch (size) {
+ case 0: // 8
+ emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
+ emith_sext(hr2, hr2, 8);
+ break;
+ case 1: // 16
+ emith_read16_r_r_offs(hr2, hr, offs2);
+ emith_sext(hr2, hr2, 16);
+ break;
+ case 2: // 32
+ emith_read_r_r_offs(hr2, hr, offs2);
+ emith_ror(hr2, hr2, 16);
+ break;
+ }
+ rcache_free_tmp(hr);
+ return hr2;
+ }
+
+ ram_check = 0;
+ }
+
+ hr = rcache_get_reg_arg(0, rs);
+ if (offs != 0)
+ emith_add_r_imm(hr, offs);
+ hr = emit_memhandler_read_(size, ram_check);
+ hr2 = rcache_get_reg(rd, RC_GR_WRITE);
+ if (size != 2) {
+ emith_sext(hr2, hr, (size == 1) ? 16 : 8);
+ } else
+ emith_move_r_r(hr2, hr);
+ rcache_free_tmp(hr);
+
+ return hr2;
+}
+
+static void emit_memhandler_write(int size)
+{
+ int ctxr;
+ host_arg2reg(ctxr, 2);
+ if (reg_map_g2h[SHR_SR] != -1)
+ emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
+
+ rcache_clean();
+
+ switch (size) {
+ case 0: // 8
+ // XXX: consider inlining sh2_drc_write8
+ emith_call(sh2_drc_write8);
+ break;
+ case 1: // 16
+ emith_call(sh2_drc_write16);
+ break;
+ case 2: // 32
+ emith_move_r_r(ctxr, CONTEXT_REG);
+ emith_call(sh2_drc_write32);
+ break;
+ }
+
+ rcache_invalidate();
+ if (reg_map_g2h[SHR_SR] != -1)
+ emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
+}
+
+// @(Rx,Ry)
+static int emit_indirect_indexed_read(int rx, int ry, int size)
+{
+ int a0, t;
+ a0 = rcache_get_reg_arg(0, rx);
+ t = rcache_get_reg(ry, RC_GR_READ);
+ emith_add_r_r(a0, t);
+ return emit_memhandler_read(size);
+}
+
+// read @Rn, @rm
+static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
+{
+ int tmp;
+
+ rcache_get_reg_arg(0, rn);
+ tmp = emit_memhandler_read(size);
+ emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
+ rcache_free_tmp(tmp);
+ tmp = rcache_get_reg(rn, RC_GR_RMW);
+ emith_add_r_imm(tmp, 1 << size);
+ rcache_unlock(tmp);
+
+ rcache_get_reg_arg(0, rm);
+ *rmr = emit_memhandler_read(size);
+ *rnr = rcache_get_tmp();
+ emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
+ tmp = rcache_get_reg(rm, RC_GR_RMW);
+ emith_add_r_imm(tmp, 1 << size);
+ rcache_unlock(tmp);
+}
+
+static void emit_do_static_regs(int is_write, int tmpr)
+{
+ int i, r, count;
+
+ for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
+ r = reg_map_g2h[i];
+ if (r == -1)
+ continue;
+
+ for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
+ if (reg_map_g2h[i + 1] != r + 1)
+ break;
+ count++;
+ }
+
+ if (count > 1) {
+ // i, r point to last item
+ if (is_write)
+ emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
+ else
+ emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
+ } else {
+ if (is_write)
+ emith_ctx_write(r, i * 4);
+ else
+ emith_ctx_read(r, i * 4);
+ }
+ }
+}
+
+static void emit_block_entry(void)
+{
+ int arg0;
+
+ host_arg2reg(arg0, 0);
+
+#if (DRC_DEBUG & 8) || defined(PDB)
+ int arg1, arg2;
+ host_arg2reg(arg1, 1);
+ host_arg2reg(arg2, 2);
+
+ emit_do_static_regs(1, arg2);
+ emith_move_r_r(arg1, CONTEXT_REG);
+ emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
+ emith_call(sh2_drc_log_entry);
+ rcache_invalidate();
+#endif
+ emith_tst_r_r(arg0, arg0);
+ EMITH_SJMP_START(DCOND_EQ);
+ emith_jump_reg_c(DCOND_NE, arg0);
+ EMITH_SJMP_END(DCOND_EQ);
+}
+
+#define DELAY_SAVE_T(sr) { \
+ emith_bic_r_imm(sr, T_save); \
+ emith_tst_r_imm(sr, T); \
+ EMITH_SJMP_START(DCOND_EQ); \
+ emith_or_r_imm_c(DCOND_NE, sr, T_save); \
+ EMITH_SJMP_END(DCOND_EQ); \
+}
+
+#define FLUSH_CYCLES(sr) \
+ if (cycles > 0) { \
+ emith_sub_r_imm(sr, cycles << 12); \
+ cycles = 0; \
+ }
+
+static void *dr_get_pc_base(u32 pc, int is_slave);
+
+static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
+{
+ u32 branch_target_pc[MAX_LOCAL_BRANCHES];
+ void *branch_target_ptr[MAX_LOCAL_BRANCHES];
+ int branch_target_count = 0;
+ void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
+ u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
+ int branch_patch_count = 0;
+ u32 literal_addr[MAX_LITERALS];
+ int literal_addr_count = 0;
+ u8 op_flags[BLOCK_INSN_LIMIT];
+ struct {
+ u32 test_irq:1;
+ u32 pending_branch_direct:1;
+ u32 pending_branch_indirect:1;
+ u32 literals_disabled:1;
+ } drcf = { 0, };
+
+ // PC of current, first, last SH2 insn
+ u32 pc, base_pc, end_pc;
+ u32 end_literals;
+ void *block_entry_ptr;
+ struct block_desc *block;
+ u16 *dr_pc_base;
+ struct op_data *opd;
+ int blkid_main = 0;
+ int skip_op = 0;
+ u32 tmp, tmp2;
+ int cycles;
+ int i, v;
+ int op;
+
+ base_pc = sh2->pc;
+ drcf.literals_disabled = literal_disabled_frames != 0;
+
+ // get base/validate PC
+ dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
+ if (dr_pc_base == (void *)-1) {
+ printf("invalid PC, aborting: %08x\n", base_pc);
+ // FIXME: be less destructive
+ exit(1);
+ }
+
+ tcache_ptr = tcache_ptrs[tcache_id];
+
+ // predict tcache overflow
+ tmp = tcache_ptr - tcache_bases[tcache_id];
+ if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
+ dbg(1, "tcache %d overflow", tcache_id);
+ return NULL;
+ }
+
+ // initial passes to disassemble and analyze the block
+ scan_block(base_pc, sh2->is_slave, op_flags, &end_pc, &end_literals);
+
+ if (drcf.literals_disabled)
+ end_literals = end_pc;
+
+ block = dr_add_block(base_pc, end_literals - base_pc,
+ end_pc - base_pc, sh2->is_slave, &blkid_main);
+ if (block == NULL)
+ return NULL;
+
+ block_entry_ptr = tcache_ptr;
+ dbg(2, "== %csh2 block #%d,%d %08x-%08x -> %p", sh2->is_slave ? 's' : 'm',
+ tcache_id, blkid_main, base_pc, end_pc, block_entry_ptr);
+
+ dr_link_blocks(&block->entryp[0], tcache_id);
+
+ // collect branch_targets that don't land on delay slots
+ for (pc = base_pc, i = 0; pc < end_pc; i++, pc += 2) {
+ if (!(op_flags[i] & OF_BTARGET))
+ continue;
+ if (op_flags[i] & OF_DELAY_OP) {
+ op_flags[i] &= ~OF_BTARGET;
+ continue;
+ }
+ ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
+ }
+
+ if (branch_target_count > 0) {
+ memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
+ }
+
+ // clear stale state after compile errors
+ rcache_invalidate();
+
+ // -------------------------------------------------
+ // 3rd pass: actual compilation
+ pc = base_pc;
+ cycles = 0;
+ for (i = 0; pc < end_pc; i++)
+ {
+ u32 delay_dep_fw = 0, delay_dep_bk = 0;
+ u32 tmp3, tmp4, sr;
+
+ opd = &ops[i];
+ op = FETCH_OP(pc);
+
+#if (DRC_DEBUG & 2)
+ insns_compiled++;
+#endif
+#if (DRC_DEBUG & 4)
+ DasmSH2(sh2dasm_buff, pc, op);
+ printf("%c%08x %04x %s\n", (op_flags[i] & OF_BTARGET) ? '*' : ' ',
+ pc, op, sh2dasm_buff);
+#endif
+
+ if ((op_flags[i] & OF_BTARGET) || pc == base_pc)
+ {
+ if (pc != base_pc)
+ {
+ sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
+ FLUSH_CYCLES(sr);
+ rcache_flush();
+
+ // make block entry
+ v = block->entry_count;
+ if (v < ARRAY_SIZE(block->entryp)) {
+ block->entryp[v].pc = pc;
+ block->entryp[v].tcache_ptr = tcache_ptr;
+ block->entryp[v].links = NULL;
+#if (DRC_DEBUG & 2)
+ block->entryp[v].block = block;
+#endif
+ add_to_hashlist(&block->entryp[v], tcache_id);
+ block->entry_count++;
+
+ dbg(2, "-- %csh2 block #%d,%d entry %08x -> %p",
+ sh2->is_slave ? 's' : 'm', tcache_id, blkid_main,
+ pc, tcache_ptr);
+
+ // since we made a block entry, link any other blocks
+ // that jump to current pc
+ dr_link_blocks(&block->entryp[v], tcache_id);
+ }
+ else {
+ dbg(1, "too many entryp for block #%d,%d pc=%08x",
+ tcache_id, blkid_main, pc);
+ }
+
+ do_host_disasm(tcache_id);
+ }
+
+ v = find_in_array(branch_target_pc, branch_target_count, pc);
+ if (v >= 0)
+ branch_target_ptr[v] = tcache_ptr;
+
+ // must update PC
+ emit_move_r_imm32(SHR_PC, pc);
+ rcache_clean();
+
+ // check cycles
+ sr = rcache_get_reg(SHR_SR, RC_GR_READ);
+ emith_cmp_r_imm(sr, 0);
+ emith_jump_cond(DCOND_LE, sh2_drc_exit);
+ do_host_disasm(tcache_id);
+ rcache_unlock_all();
+ }
+
+#ifdef DRC_CMP
+ if (!(op_flags[i] & OF_DELAY_OP)) {
+ emit_move_r_imm32(SHR_PC, pc);
+ sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
+ FLUSH_CYCLES(sr);
+ rcache_clean();
+
+ tmp = rcache_used_hreg_mask();
+ emith_save_caller_regs(tmp);
+ emit_do_static_regs(1, 0);
+ emith_pass_arg_r(0, CONTEXT_REG);
+ emith_call(do_sh2_cmp);
+ emith_restore_caller_regs(tmp);
+ }
+#endif
+
+ pc += 2;
+
+ if (skip_op > 0) {
+ skip_op--;
+ continue;
+ }
+
+ if (op_flags[i] & OF_DELAY_OP)
+ {
+ // handle delay slot dependencies
+ delay_dep_fw = opd->dest & ops[i-1].source;
+ delay_dep_bk = opd->source & ops[i-1].dest;
+ if (delay_dep_fw & BITMASK1(SHR_T)) {
+ sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
+ DELAY_SAVE_T(sr);
+ }
+ if (delay_dep_bk & BITMASK1(SHR_PC)) {
+ if (opd->op != OP_LOAD_POOL && opd->op != OP_MOVA) {
+ // can only be those 2 really..
+ elprintf_sh2(sh2, EL_ANOMALY,
+ "drc: illegal slot insn %04x @ %08x?", op, pc - 2);
+ }
+ if (opd->imm != 0)
+ ; // addr already resolved somehow
+ else {
+ switch (ops[i-1].op) {
+ case OP_BRANCH:
+ emit_move_r_imm32(SHR_PC, ops[i-1].imm);
+ break;
+ case OP_BRANCH_CT:
+ case OP_BRANCH_CF:
+ tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
+ sr = rcache_get_reg(SHR_SR, RC_GR_READ);
+ emith_move_r_imm(tmp, pc);
+ emith_tst_r_imm(sr, T);
+ tmp2 = ops[i-1].op == OP_BRANCH_CT ? DCOND_NE : DCOND_EQ;
+ emith_move_r_imm_c(tmp2, tmp, ops[i-1].imm);
+ break;
+ // case OP_BRANCH_R OP_BRANCH_RF - PC already loaded
+ }
+ }
+ }
+ //if (delay_dep_fw & ~BITMASK1(SHR_T))
+ // dbg(1, "unhandled delay_dep_fw: %x", delay_dep_fw & ~BITMASK1(SHR_T));
+ if (delay_dep_bk & ~BITMASK2(SHR_PC, SHR_PR))
+ dbg(1, "unhandled delay_dep_bk: %x", delay_dep_bk);
+ }
+
+ switch (opd->op)
+ {
+ case OP_BRANCH:
+ case OP_BRANCH_CT:
+ case OP_BRANCH_CF:
+ if (opd->dest & BITMASK1(SHR_PR))
+ emit_move_r_imm32(SHR_PR, pc + 2);
+ drcf.pending_branch_direct = 1;
+ goto end_op;
+
+ case OP_BRANCH_R:
+ if (opd->dest & BITMASK1(SHR_PR))
+ emit_move_r_imm32(SHR_PR, pc + 2);
+ emit_move_r_r(SHR_PC, opd->rm);
+ drcf.pending_branch_indirect = 1;
+ goto end_op;
+
+ case OP_BRANCH_RF:
+ tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
+ tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
+ if (opd->dest & BITMASK1(SHR_PR)) {
+ tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
+ emith_move_r_imm(tmp3, pc + 2);
+ emith_add_r_r_r(tmp, tmp2, tmp3);
+ }
+ else {
+ emith_move_r_r(tmp, tmp2);
+ emith_add_r_imm(tmp, pc + 2);
+ }
+ drcf.pending_branch_indirect = 1;
+ goto end_op;
+
+ case OP_SLEEP:
+ printf("TODO sleep\n");
+ goto end_op;
+
+ case OP_RTE:
+ // pop PC
+ emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
+ // pop SR
+ tmp = rcache_get_reg_arg(0, SHR_SP);
+ emith_add_r_imm(tmp, 4);
+ tmp = emit_memhandler_read(2);
+ sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
+ emith_write_sr(sr, tmp);
+ rcache_free_tmp(tmp);
+ tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
+ emith_add_r_imm(tmp, 4*2);
+ drcf.test_irq = 1;
+ drcf.pending_branch_indirect = 1;
+ goto end_op;
+
+ case OP_LOAD_POOL:
+#if PROPAGATE_CONSTANTS
+ if (opd->imm != 0 && opd->imm < end_literals
+ && literal_addr_count < MAX_LITERALS)
+ {
+ ADD_TO_ARRAY(literal_addr, literal_addr_count, opd->imm,);
+ if (opd->size == 2)
+ tmp = FETCH32(opd->imm);
+ else
+ tmp = (u32)(int)(signed short)FETCH_OP(opd->imm);
+ gconst_new(GET_Rn(), tmp);
+ }
+ else
+#endif
+ {
+ tmp = rcache_get_tmp_arg(0);
+ if (opd->imm != 0)
+ emith_move_r_imm(tmp, opd->imm);
+ else {
+ // have to calculate read addr from PC
+ tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
+ if (opd->size == 2) {
+ emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
+ emith_bic_r_imm(tmp, 3);
+ }
+ else
+ emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 2);
+ }
+ tmp2 = emit_memhandler_read(opd->size);
+ tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
+ if (opd->size == 2)
+ emith_move_r_r(tmp3, tmp2);
+ else
+ emith_sext(tmp3, tmp2, 16);
+ rcache_free_tmp(tmp2);
+ }
+ goto end_op;
+
+ case OP_MOVA:
+ if (opd->imm != 0)
+ emit_move_r_imm32(SHR_R0, opd->imm);
+ else {
+ tmp = rcache_get_reg(SHR_R0, RC_GR_WRITE);
+ tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
+ emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
+ emith_bic_r_imm(tmp, 3);
+ }
+ goto end_op;
+ }
+
+ switch ((op >> 12) & 0x0f)
+ {
+ /////////////////////////////////////////////
+ case 0x00:
+ switch (op & 0x0f)
+ {
+ case 0x02:
+ tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
+ switch (GET_Fx())
+ {
+ case 0: // STC SR,Rn 0000nnnn00000010
+ tmp2 = SHR_SR;
+ break;
+ case 1: // STC GBR,Rn 0000nnnn00010010
+ tmp2 = SHR_GBR;
+ break;
+ case 2: // STC VBR,Rn 0000nnnn00100010
+ tmp2 = SHR_VBR;
+ break;
+ default: