+ op = p32x_sh2_read16(pc, sh2);
+
+#if (DRC_DEBUG & 3)
+ insns_compiled++;
+#if (DRC_DEBUG & 2)
+ DasmSH2(sh2dasm_buff, pc, op);
+ printf("%08x %04x %s\n", pc, op, sh2dasm_buff);
+#endif
+#endif
+
+ pc += 2;
+ cycles++;
+
+ switch ((op >> 12) & 0x0f)
+ {
+ case 0x00:
+ switch (op & 0x0f) {
+ case 0x03:
+ CHECK_UNHANDLED_BITS(0xd0);
+ // BRAF Rm 0000mmmm00100011
+ // BSRF Rm 0000mmmm00000011
+ DELAYED_OP;
+ if (!(op & 0x20))
+ emit_move_r_imm32(SHR_PR, pc + 2);
+ emit_braf((op >> 8) & 0x0f, pc + 2);
+ cycles++;
+ goto end_op;
+ case 0x09:
+ CHECK_UNHANDLED_BITS(0xf0);
+ // NOP 0000000000001001
+ goto end_op;
+ case 0x0b:
+ CHECK_UNHANDLED_BITS(0xd0);
+ DELAYED_OP;
+ if (!(op & 0x20)) {
+ // RTS 0000000000001011
+ emit_move_r_r(SHR_PPC, SHR_PR);
+ cycles++;
+ } else {
+ // RTE 0000000000101011
+ //emit_move_r_r(SHR_PC, SHR_PR);
+ emit_move_r_imm32(SHR_PC, pc - 2);
+ emith_pass_arg_r(0, CONTEXT_REG);
+ emith_pass_arg_imm(1, op);
+ emith_call(sh2_do_op);
+ emit_move_r_r(SHR_PPC, SHR_PC);
+ test_irq = 1;
+ cycles += 3;
+ }
+ goto end_op;
+ }
+ goto default_;
+
+ case 0x04:
+ switch (op & 0x0f) {
+ case 0x07:
+ if ((op & 0xf0) != 0)
+ goto default_;
+ // LDC.L @Rm+,SR 0100mmmm00000111
+ test_irq = 1;
+ goto default_;
+ case 0x0b:
+ if ((op & 0xd0) != 0)
+ goto default_;
+ // JMP @Rm 0100mmmm00101011
+ // JSR @Rm 0100mmmm00001011
+ DELAYED_OP;
+ if (!(op & 0x20))
+ emit_move_r_imm32(SHR_PR, pc + 2);
+ emit_move_r_r(SHR_PPC, (op >> 8) & 0x0f);
+ cycles++;
+ goto end_op;
+ case 0x0e:
+ if ((op & 0xf0) != 0)
+ goto default_;
+ // LDC Rm,SR 0100mmmm00001110
+ test_irq = 1;
+ goto default_;
+ }
+ goto default_;
+
+ case 0x08:
+ switch (op & 0x0f00) {
+ // BT/S label 10001101dddddddd
+ case 0x0d00:
+ // BF/S label 10001111dddddddd
+ case 0x0f00:
+ DELAYED_OP;
+ cycles--;
+ // fallthrough
+ // BT label 10001001dddddddd
+ case 0x0900:
+ // BF label 10001011dddddddd
+ case 0x0b00:
+ tmp = ((signed int)(op << 24) >> 23);
+ tmp2 = delayed_op ? SHR_PPC : SHR_PC;
+ emit_move_r_imm32(tmp2, pc + (delayed_op ? 2 : 0));
+ emith_test_t();
+ EMITH_CONDITIONAL(emit_move_r_imm32(tmp2, pc + tmp + 2), (op & 0x0200) ? 1 : 0);
+ cycles += 2;
+ if (!delayed_op)
+ goto end_block;
+ goto end_op;
+ }
+ goto default_;
+
+ case 0x0a:
+ // BRA label 1010dddddddddddd
+ DELAYED_OP;
+ do_bra:
+ tmp = ((signed int)(op << 20) >> 19);
+ emit_move_r_imm32(SHR_PPC, pc + tmp + 2);
+ cycles++;
+ break;
+
+ case 0x0b:
+ // BSR label 1011dddddddddddd
+ DELAYED_OP;
+ emit_move_r_imm32(SHR_PR, pc + 2);
+ goto do_bra;
+
+ default:
+ default_:
+ emit_move_r_imm32(SHR_PC, pc - 2);
+ emith_pass_arg_r(0, CONTEXT_REG);
+ emith_pass_arg_imm(1, op);
+ emith_call(sh2_do_op);
+ break;
+ }
+
+end_op:
+ if (delayed_op == 1)
+ emit_move_r_r(SHR_PC, SHR_PPC);
+
+ if (test_irq && delayed_op != 2) {
+ emith_pass_arg_r(0, CONTEXT_REG);
+ emith_call(sh2_test_irq);
+ break;
+ }
+ if (delayed_op == 1)
+ break;
+
+ do_host_disasm(tcache_id);
+ }
+
+end_block:
+ this_block->end_addr = pc;
+
+ // mark memory blocks as containing compiled code
+ if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
+ // data array, BIOS
+ u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
+ tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
+ tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT;
+ Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1;
+ for (++tmp; tmp < tmp2; tmp++) {
+ if (drcblk[tmp])
+ break; // dont overwrite overlay block
+ drcblk[tmp] = blkid << 1;
+ }
+ }
+ else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
+ tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
+ tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
+ Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1;
+ for (++tmp; tmp < tmp2; tmp++) {
+ if (Pico32xMem->drcblk_ram[tmp])
+ break;
+ Pico32xMem->drcblk_ram[tmp] = blkid << 1;
+ }
+ }
+
+ if (reg_map_g2h[SHR_SR] == -1) {
+ emith_ctx_sub(cycles << 12, SHR_SR * 4);
+ } else
+ emith_sub_r_imm(reg_map_g2h[SHR_SR], cycles << 12);
+ emith_jump(sh2_drc_exit);
+ tcache_ptrs[tcache_id] = tcache_ptr;
+
+ do_host_disasm(tcache_id);
+ dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
+ tcache_id, block_counts[tcache_id],
+ tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
+ insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled);
+ if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
+ dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
+ return block_entry;
+/*
+unimplemented:
+ // last op
+ do_host_disasm(tcache_id);
+ exit(1);
+*/
+}
+
+void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
+{
+ while (((signed int)sh2->sr >> 12) > 0)
+ {
+ void *block = NULL;
+ block_desc *bd = NULL;
+
+ // FIXME: must avoid doing it so often..
+ sh2_test_irq(sh2);
+
+ // we have full block id tables for data_array and RAM
+ // BIOS goes to data_array table too
+ if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) {
+ int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT];
+ if (blkid & 1) {
+ bd = &block_tables[1 + sh2->is_slave][blkid >> 1];
+ block = bd->tcache_ptr;
+ }
+ }
+ // RAM
+ else if ((sh2->pc & 0xc6000000) == 0x06000000) {
+ int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT];
+ if (blkid & 1) {
+ bd = &block_tables[0][blkid >> 1];
+ block = bd->tcache_ptr;
+ }
+ }
+ // ROM
+ else if ((sh2->pc & 0xc6000000) == 0x02000000) {
+ bd = HASH_FUNC(hash_table, sh2->pc);
+
+ if (bd != NULL) {
+ if (bd->addr == sh2->pc)
+ block = bd->tcache_ptr;
+ else
+ block = dr_find_block(bd, sh2->pc);
+ }
+ }
+
+ if (block == NULL)
+ block = sh2_translate(sh2, bd);
+
+ dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
+ sh2->pc, block, (signed int)sh2->sr >> 12);
+#if (DRC_DEBUG & 1)
+ if (bd != NULL)
+ bd->refcount++;
+#endif
+ sh2_drc_entry(sh2, block);
+ }
+}
+
+static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a)
+{
+ u16 id = *p >> 1;
+ block_desc *bd = btab + id;
+
+ dbg(1, " killing block %08x", bd->addr);
+ bd->addr = bd->end_addr = 0;
+
+ while (p > drcblk && (p[-1] >> 1) == id)
+ p--;
+
+ // check for possible overlay block
+ if (p > 0 && p[-1] != 0) {
+ bd = btab + (p[-1] >> 1);
+ if (bd->addr <= a && a < bd->end_addr)
+ sh2_smc_rm_block(drcblk, p - 1, btab, a);
+ }
+
+ do {
+ *p++ = 0;
+ }
+ while ((*p >> 1) == id);
+}
+
+void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
+{
+ u16 *drcblk = Pico32xMem->drcblk_ram;
+ u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT);
+
+ dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
+ sh2_smc_rm_block(drcblk, p, block_tables[0], a);
+}
+
+void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
+{
+ u16 *drcblk = Pico32xMem->drcblk_da[cpuid];
+ u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT);
+
+ dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
+ sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a);