+ /* By default assume it works or have/need unaligned instructions. */
+ jit_cpu.sll_delay = jit_cpu.cop1_delay = jit_cpu.lwl_lwr_delay =
+ jit_cpu.unaligned = 1;
+
+#if defined(__linux__)
+ FILE *fp;
+ char *ptr;
+ char buf[128];
+
+ if ((fp = fopen("/proc/cpuinfo", "r")) != NULL) {
+ while (fgets(buf, sizeof(buf), fp)) {
+ if (strncmp(buf, "isa\t\t\t: ", 8) == 0) {
+ if ((ptr = strstr(buf + 9, "mips64r")))
+ jit_cpu.release = strtoul(ptr + 7, NULL, 10);
+ break;
+ }
+ /* Just for some actual hardware tested. Below check
+ * for mips 1 would disable these delays anyway. */
+ if (strncmp(buf, "cpu model\t\t: ", 13) == 0) {
+ /* ICT Loongson-2 V0.3 FPU V0.1 */
+ if (strstr(buf + 13, "FPU V0.1"))
+ jit_cpu.sll_delay = jit_cpu.cop1_delay = 0;
+ /* Cavium Octeon III V0.2 FPU V0.0 */
+ else if (strstr(buf + 13, "FPU V0.0"))
+ jit_cpu.sll_delay = jit_cpu.cop1_delay = 0;
+ /* Cavium Octeon II V0.1 */
+ else if (strstr(buf + 13, " II "))
+ jit_cpu.sll_delay = jit_cpu.cop1_delay = 0;
+ break;
+ }
+ }
+ fclose(fp);
+ }
+#endif
+#if __mips_isa_rev
+ if (!jit_cpu.release)
+ jit_cpu.release = __mips_isa_rev;
+#elif defined _MIPS_ARCH
+ if (!jit_cpu.release)
+ jit_cpu.release = strtoul(&_MIPS_ARCH[4], NULL, 10);
+#elif defined(__mips) && __mips < 6
+ if (!jit_cpu.release)
+ jit_cpu.release = __mips;
+#endif
+ /* Assume all mips 1 and 2, or detected as release 1 or 2 have this
+ * problem */
+ /* Note that jit_cpu is global, and can be overriden, that is, add
+ * the C code "jit_cpu.cop1_delay = 1;" after the call to init_jit()
+ * if it is functional. */
+ if (jit_cpu.cop1_delay && jit_cpu.release < 3)
+ jit_cpu.cop1_delay = 0;
+ if (jit_cpu.sll_delay && jit_cpu.release < 3)
+ jit_cpu.sll_delay = 0;
+ if (jit_cpu.lwl_lwr_delay && jit_cpu.release < 2)
+ jit_cpu.lwl_lwr_delay = 0;
+ if (jit_cpu.release >= 6)
+ jit_cpu.unaligned = 0;