+ union code c = block->opcode_list[offset].c;
+ u32 flags = block->opcode_list[offset].flags;
+ bool is_tagged = LIGHTREC_FLAGS_GET_IO_MODE(flags);
+ u32 lut_entry;
+ u8 zero;
+
+ jit_note(__FILE__, __LINE__);
+
+ lightrec_clean_reg_if_loaded(reg_cache, _jit, c.i.rs, false);
+
+ if (read_rt && likely(c.i.rt))
+ lightrec_clean_reg_if_loaded(reg_cache, _jit, c.i.rt, true);
+ else if (load_rt)
+ lightrec_clean_reg_if_loaded(reg_cache, _jit, c.i.rt, false);
+
+ if (op_flag_load_delay(flags) && !state->no_load_delay) {
+ /* Clear state->in_delay_slot_n. This notifies the lightrec_rw
+ * wrapper that it should write the REG_TEMP register instead of
+ * the actual output register of the opcode. */
+ zero = lightrec_alloc_reg_in(reg_cache, _jit, 0, 0);
+ jit_stxi_c(offsetof(struct lightrec_state, in_delay_slot_n),
+ LIGHTREC_REG_STATE, zero);
+ lightrec_free_reg(reg_cache, zero);
+ }
+
+ if (is_tagged) {
+ call_to_c_wrapper(state, block, c.opcode, C_WRAPPER_RW);
+ } else {
+ lut_entry = lightrec_get_lut_entry(block);
+ call_to_c_wrapper(state, block, (lut_entry << 16) | offset,
+ C_WRAPPER_RW_GENERIC);
+ }
+}
+
+static u32 rec_ram_mask(const struct lightrec_state *state)
+{
+ return (RAM_SIZE << (state->mirrors_mapped * 2)) - 1;
+}
+
+static u32 rec_io_mask(const struct lightrec_state *state)
+{
+ u32 length = state->maps[PSX_MAP_HW_REGISTERS].length;
+
+ return 0x1f800000 | GENMASK(31 - clz32(length - 1), 0);
+}
+
+static void rec_store_memory(struct lightrec_cstate *cstate,
+ const struct block *block,
+ u16 offset, jit_code_t code,
+ jit_code_t swap_code,
+ uintptr_t addr_offset, u32 addr_mask,
+ bool invalidate)
+{
+ const struct lightrec_state *state = cstate->state;
+ struct regcache *reg_cache = cstate->reg_cache;
+ struct opcode *op = &block->opcode_list[offset];
+ jit_state_t *_jit = block->_jit;
+ union code c = op->c;
+ u8 rs, rt, tmp = 0, tmp2 = 0, tmp3, addr_reg, addr_reg2;
+ s16 imm = (s16)c.i.imm;
+ s32 simm = (s32)imm << (1 - lut_is_32bit(state));
+ s32 lut_offt = offsetof(struct lightrec_state, code_lut);
+ bool no_mask = op_flag_no_mask(op->flags);
+ bool add_imm = c.i.imm &&
+ (c.i.op == OP_META_SWU
+ || (!state->mirrors_mapped && !no_mask) || (invalidate &&
+ ((imm & 0x3) || simm + lut_offt != (s16)(simm + lut_offt))));
+ bool need_tmp = !no_mask || add_imm || invalidate;
+ bool swc2 = c.i.op == OP_SWC2;
+ u8 in_reg = swc2 ? REG_TEMP : c.i.rt;
+ s8 reg_imm;
+
+ rs = lightrec_alloc_reg_in(reg_cache, _jit, c.i.rs, 0);
+ if (need_tmp)
+ tmp = lightrec_alloc_reg_temp(reg_cache, _jit);
+
+ addr_reg = rs;
+
+ if (add_imm) {
+ jit_addi(tmp, addr_reg, (s16)c.i.imm);
+ lightrec_free_reg(reg_cache, rs);
+ addr_reg = tmp;
+ imm = 0;
+ } else if (simm) {
+ lut_offt += simm;
+ }
+
+ if (!no_mask) {
+ reg_imm = lightrec_alloc_reg_temp_with_value(reg_cache, _jit,
+ addr_mask);
+
+ jit_andr(tmp, addr_reg, reg_imm);
+ addr_reg = tmp;
+
+ lightrec_free_reg(reg_cache, reg_imm);
+ }
+
+ if (addr_offset) {
+ reg_imm = lightrec_alloc_reg_temp_with_value(reg_cache, _jit,
+ addr_offset);
+ tmp2 = lightrec_alloc_reg_temp(reg_cache, _jit);
+ jit_addr(tmp2, addr_reg, reg_imm);
+ addr_reg2 = tmp2;
+
+ lightrec_free_reg(reg_cache, reg_imm);
+ } else {
+ addr_reg2 = addr_reg;
+ }
+
+ rt = lightrec_alloc_reg_in(reg_cache, _jit, in_reg, 0);
+
+ if (is_big_endian() && swap_code && in_reg) {
+ tmp3 = lightrec_alloc_reg_temp(reg_cache, _jit);
+
+ jit_new_node_ww(swap_code, tmp3, rt);
+
+ if (c.i.op == OP_META_SWU)
+ jit_unstr(addr_reg2, tmp3, LIGHTNING_UNALIGNED_32BIT);
+ else
+ jit_new_node_www(code, imm, addr_reg2, tmp3);
+
+ lightrec_free_reg(reg_cache, tmp3);
+ } else if (c.i.op == OP_META_SWU) {
+ jit_unstr(addr_reg2, rt, LIGHTNING_UNALIGNED_32BIT);
+ } else {
+ jit_new_node_www(code, imm, addr_reg2, rt);
+ }
+
+ lightrec_free_reg(reg_cache, rt);
+
+ if (invalidate) {
+ tmp3 = lightrec_alloc_reg_in(reg_cache, _jit, 0, 0);
+
+ if (c.i.op != OP_SW) {
+ jit_andi(tmp, addr_reg, ~3);
+ addr_reg = tmp;
+ }
+
+ if (!lut_is_32bit(state)) {
+ jit_lshi(tmp, addr_reg, 1);
+ addr_reg = tmp;
+ }
+
+ if (addr_reg == rs && c.i.rs == 0) {
+ addr_reg = LIGHTREC_REG_STATE;
+ } else {
+ jit_add_state(tmp, addr_reg);
+ addr_reg = tmp;
+ }
+
+ if (lut_is_32bit(state))
+ jit_stxi_i(lut_offt, addr_reg, tmp3);
+ else
+ jit_stxi(lut_offt, addr_reg, tmp3);
+
+ lightrec_free_reg(reg_cache, tmp3);
+ }
+
+ if (addr_offset)
+ lightrec_free_reg(reg_cache, tmp2);
+ if (need_tmp)
+ lightrec_free_reg(reg_cache, tmp);
+ lightrec_free_reg(reg_cache, rs);
+}
+
+static void rec_store_ram(struct lightrec_cstate *cstate,
+ const struct block *block,
+ u16 offset, jit_code_t code,
+ jit_code_t swap_code, bool invalidate)
+{
+ const struct lightrec_state *state = cstate->state;
+
+ _jit_note(block->_jit, __FILE__, __LINE__);
+
+ return rec_store_memory(cstate, block, offset, code, swap_code,
+ state->offset_ram, rec_ram_mask(state),
+ invalidate);
+}
+
+static void rec_store_scratch(struct lightrec_cstate *cstate,
+ const struct block *block, u16 offset,
+ jit_code_t code, jit_code_t swap_code)
+{
+ _jit_note(block->_jit, __FILE__, __LINE__);
+
+ return rec_store_memory(cstate, block, offset, code, swap_code,
+ cstate->state->offset_scratch,
+ 0x1fffffff, false);
+}
+
+static void rec_store_io(struct lightrec_cstate *cstate,
+ const struct block *block, u16 offset,
+ jit_code_t code, jit_code_t swap_code)
+{
+ _jit_note(block->_jit, __FILE__, __LINE__);
+
+ return rec_store_memory(cstate, block, offset, code, swap_code,
+ cstate->state->offset_io,
+ rec_io_mask(cstate->state), false);
+}
+
+static void rec_store_direct_no_invalidate(struct lightrec_cstate *cstate,
+ const struct block *block,
+ u16 offset, jit_code_t code,
+ jit_code_t swap_code)
+{
+ const struct lightrec_state *state = cstate->state;
+ struct regcache *reg_cache = cstate->reg_cache;
+ union code c = block->opcode_list[offset].c;
+ jit_state_t *_jit = block->_jit;