- warm_ret = warm_init();
- have_warm = warm_ret == 0;
- warm_change_cb_upper(WCB_B_BIT, 1);
-
- /* some firmwares have sys clk on PLL0, we can't adjust CPU clock
- * by reprogramming the PLL0 then, as it overclocks system bus */
- if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000)
- cpu_clock_allowed = 1;
- else {
- cpu_clock_allowed = 0;
- fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n",
- memregl[0xf000>>2]);
- }
-
- /* find what PLL1 runs at, for the timer */
- rate = decode_pll(memregl[0xf008>>2]);
- printf("PLL1 @ %dHz\n", rate);
-
- /* setup timer */
- timer_div = (rate + 500000) / 1000000;
- timer_div2 = 0;
- while (timer_div > 256) {
- timer_div /= 2;
- timer_div2++;
- }
- if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) {
- int timer_rate = (rate >> timer_div2) / timer_div;
- if (TIMER_REG(0x08) & 8) {
- fprintf(stderr, "warning: timer in use, overriding!\n");
- timer_cleanup();
- }
- if (timer_rate != 1000000)
- fprintf(stderr, "warning: timer drift %d us\n", timer_rate - 1000000);
-
- timer_div2 = (timer_div2 + 3) & 3;
- TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1 */
- TIMER_REG(0x40) = 0x0c; /* clocks on */
- TIMER_REG(0x08) = 0x68 | timer_div2; /* run timer, clear irq, latch value */
- }
- else
- fprintf(stderr, "warning: could not make use of timer\n");
-