+ u32 v;
+ u32 mdiv, pdiv, sdiv = 0;
+#ifdef WIZ_BUILD
+ #define SYS_CLK_FREQ 27
+ // m = MDIV, p = PDIV, s = SDIV
+ pdiv = 9;
+ mdiv = (MHZ * pdiv) / SYS_CLK_FREQ;
+ mdiv &= 0x3ff;
+ v = (pdiv<<18) | (mdiv<<8) | sdiv;
+
+ gpsp_gp2x_memregl[0xf004>>2] = v;
+ gpsp_gp2x_memregl[0xf07c>>2] |= 0x8000;
+ while (gpsp_gp2x_memregl[0xf07c>>2] & 0x8000)
+ ;
+#else
+ #define SYS_CLK_FREQ 7372800
+ // m = MDIV + 8, p = PDIV + 2, s = SDIV
+ pdiv = 3;
+ mdiv = (MHZ * pdiv * 1000000) / SYS_CLK_FREQ;
+ mdiv &= 0xff;
+ v = ((mdiv-8)<<8) | ((pdiv-2)<<2) | sdiv;
+ gpsp_gp2x_memregs[0x910>>1] = v;