-static void cop0_assemble(int i,struct regstat *i_regs)
-{
- if(opcode2[i]==0) // MFC0
- {
- signed char t=get_reg(i_regs->regmap,rt1[i]);
- u_int copr=(source[i]>>11)&0x1f;
- //assert(t>=0); // Why does this happen? OOT is weird
- if(t>=0&&rt1[i]!=0) {
- emit_readword(®_cop0[copr],t);
- }
- }
- else if(opcode2[i]==4) // MTC0
- {
- signed char s=get_reg(i_regs->regmap,rs1[i]);
- char copr=(source[i]>>11)&0x1f;
- assert(s>=0);
- wb_register(rs1[i],i_regs->regmap,i_regs->dirty);
- if(copr==9||copr==11||copr==12||copr==13) {
- emit_readword(&last_count,HOST_TEMPREG);
- emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
- emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
- emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
- emit_writeword(HOST_CCREG,&Count);
- }
- // What a mess. The status register (12) can enable interrupts,
- // so needs a special case to handle a pending interrupt.
- // The interrupt must be taken immediately, because a subsequent
- // instruction might disable interrupts again.
- if(copr==12||copr==13) {
- if (is_delayslot) {
- // burn cycles to cause cc_interrupt, which will
- // reschedule next_interupt. Relies on CCREG from above.
- assem_debug("MTC0 DS %d\n", copr);
- emit_writeword(HOST_CCREG,&last_count);
- emit_movimm(0,HOST_CCREG);
- emit_storereg(CCREG,HOST_CCREG);
- emit_loadreg(rs1[i],1);
- emit_movimm(copr,0);
- emit_call(pcsx_mtc0_ds);
- emit_loadreg(rs1[i],s);
- return;
- }
- emit_movimm(start+i*4+4,HOST_TEMPREG);
- emit_writeword(HOST_TEMPREG,&pcaddr);
- emit_movimm(0,HOST_TEMPREG);
- emit_writeword(HOST_TEMPREG,&pending_exception);
- }
- //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
- //else
- if(s==HOST_CCREG)
- emit_loadreg(rs1[i],1);
- else if(s!=1)
- emit_mov(s,1);
- emit_movimm(copr,0);
- emit_call(pcsx_mtc0);
- if(copr==9||copr==11||copr==12||copr==13) {
- emit_readword(&Count,HOST_CCREG);
- emit_readword(&next_interupt,HOST_TEMPREG);
- emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
- emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
- emit_writeword(HOST_TEMPREG,&last_count);
- emit_storereg(CCREG,HOST_CCREG);
- }
- if(copr==12||copr==13) {
- assert(!is_delayslot);
- emit_readword(&pending_exception,14);
- emit_test(14,14);
- emit_jne(&do_interrupt);
- }
- emit_loadreg(rs1[i],s);
- if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
- emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
- }
- else
- {
- assert(opcode2[i]==0x10);
- //if((source[i]&0x3f)==0x10) // RFE
- {
- emit_readword(&Status,0);
- emit_andimm(0,0x3c,1);
- emit_andimm(0,~0xf,0);
- emit_orrshr_imm(1,2,0);
- emit_writeword(0,&Status);
- }
- }
-}
-
-static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
-{
- switch (copr) {
- case 1:
- case 3:
- case 5:
- case 8:
- case 9:
- case 10:
- case 11:
- emit_readword(®_cop2d[copr],tl);
- emit_signextend16(tl,tl);
- emit_writeword(tl,®_cop2d[copr]); // hmh
- break;
- case 7:
- case 16:
- case 17:
- case 18:
- case 19:
- emit_readword(®_cop2d[copr],tl);
- emit_andimm(tl,0xffff,tl);
- emit_writeword(tl,®_cop2d[copr]);
- break;
- case 15:
- emit_readword(®_cop2d[14],tl); // SXY2
- emit_writeword(tl,®_cop2d[copr]);
- break;
- case 28:
- case 29:
- emit_readword(®_cop2d[9],temp);
- emit_testimm(temp,0x8000); // do we need this?
- emit_andimm(temp,0xf80,temp);
- emit_andne_imm(temp,0,temp);
- emit_shrimm(temp,7,tl);
- emit_readword(®_cop2d[10],temp);
- emit_testimm(temp,0x8000);
- emit_andimm(temp,0xf80,temp);
- emit_andne_imm(temp,0,temp);
- emit_orrshr_imm(temp,2,tl);
- emit_readword(®_cop2d[11],temp);
- emit_testimm(temp,0x8000);
- emit_andimm(temp,0xf80,temp);
- emit_andne_imm(temp,0,temp);
- emit_orrshl_imm(temp,3,tl);
- emit_writeword(tl,®_cop2d[copr]);
- break;
- default:
- emit_readword(®_cop2d[copr],tl);
- break;
- }
-}
-
-static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
-{
- switch (copr) {
- case 15:
- emit_readword(®_cop2d[13],temp); // SXY1
- emit_writeword(sl,®_cop2d[copr]);
- emit_writeword(temp,®_cop2d[12]); // SXY0
- emit_readword(®_cop2d[14],temp); // SXY2
- emit_writeword(sl,®_cop2d[14]);
- emit_writeword(temp,®_cop2d[13]); // SXY1
- break;
- case 28:
- emit_andimm(sl,0x001f,temp);
- emit_shlimm(temp,7,temp);
- emit_writeword(temp,®_cop2d[9]);
- emit_andimm(sl,0x03e0,temp);
- emit_shlimm(temp,2,temp);
- emit_writeword(temp,®_cop2d[10]);
- emit_andimm(sl,0x7c00,temp);
- emit_shrimm(temp,3,temp);
- emit_writeword(temp,®_cop2d[11]);
- emit_writeword(sl,®_cop2d[28]);
- break;
- case 30:
- emit_movs(sl,temp);
- emit_mvnmi(temp,temp);
-#ifdef HAVE_ARMV5
- emit_clz(temp,temp);
-#else
- emit_movs(temp,HOST_TEMPREG);
- emit_movimm(0,temp);
- emit_jeq((int)out+4*4);
- emit_addpl_imm(temp,1,temp);
- emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
- emit_jns((int)out-2*4);
-#endif
- emit_writeword(sl,®_cop2d[30]);
- emit_writeword(temp,®_cop2d[31]);
- break;
- case 31:
- break;
- default:
- emit_writeword(sl,®_cop2d[copr]);
- break;
- }
-}
-
-static void cop2_assemble(int i,struct regstat *i_regs)
-{
- u_int copr=(source[i]>>11)&0x1f;
- signed char temp=get_reg(i_regs->regmap,-1);
- if (opcode2[i]==0) { // MFC2
- signed char tl=get_reg(i_regs->regmap,rt1[i]);
- if(tl>=0&&rt1[i]!=0)
- cop2_get_dreg(copr,tl,temp);
- }
- else if (opcode2[i]==4) { // MTC2
- signed char sl=get_reg(i_regs->regmap,rs1[i]);
- cop2_put_dreg(copr,sl,temp);
- }
- else if (opcode2[i]==2) // CFC2
- {
- signed char tl=get_reg(i_regs->regmap,rt1[i]);
- if(tl>=0&&rt1[i]!=0)
- emit_readword(®_cop2c[copr],tl);
- }
- else if (opcode2[i]==6) // CTC2
- {
- signed char sl=get_reg(i_regs->regmap,rs1[i]);
- switch(copr) {
- case 4:
- case 12:
- case 20:
- case 26:
- case 27:
- case 29:
- case 30:
- emit_signextend16(sl,temp);
- break;
- case 31:
- //value = value & 0x7ffff000;
- //if (value & 0x7f87e000) value |= 0x80000000;
- emit_shrimm(sl,12,temp);
- emit_shlimm(temp,12,temp);
- emit_testimm(temp,0x7f000000);
- emit_testeqimm(temp,0x00870000);
- emit_testeqimm(temp,0x0000e000);
- emit_orrne_imm(temp,0x80000000,temp);
- break;
- default:
- temp=sl;
- break;
- }
- emit_writeword(temp,®_cop2c[copr]);
- assert(sl>=0);
- }
-}
-