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drc: remove unnecessary cache flushing
[pcsx_rearmed.git]
/
libpcsxcore
/
new_dynarec
/
assem_arm.h
diff --git
a/libpcsxcore/new_dynarec/assem_arm.h
b/libpcsxcore/new_dynarec/assem_arm.h
index
7ed8caf
..
2d10ac7
100644
(file)
--- a/
libpcsxcore/new_dynarec/assem_arm.h
+++ b/
libpcsxcore/new_dynarec/assem_arm.h
@@
-9,28
+9,18
@@
#define USE_MINI_HT 1
//#define REG_PREFETCH 1
#define HAVE_CONDITIONAL_CALL 1
#define USE_MINI_HT 1
//#define REG_PREFETCH 1
#define HAVE_CONDITIONAL_CALL 1
-#define DISABLE_TLB 1
-//#define MUPEN64
-#define FORCE32 1
-#define DISABLE_COP1 1
-#define PCSX 1
#define RAM_SIZE 0x200000
#ifndef __ARM_ARCH_7A__
#define RAM_SIZE 0x200000
#ifndef __ARM_ARCH_7A__
-#define ARMv5_ONLY
//#undef CORTEX_A8_BRANCH_PREDICTION_HACK
//#undef USE_MINI_HT
#endif
//#undef CORTEX_A8_BRANCH_PREDICTION_HACK
//#undef USE_MINI_HT
#endif
-#ifndef
__ANDROID__
-#define BASE_ADDR_FIXED
1
+#ifndef
BASE_ADDR_FIXED
+#define BASE_ADDR_FIXED
0
#endif
#endif
-#ifdef FORCE32
#define REG_SHIFT 2
#define REG_SHIFT 2
-#else
-#define REG_SHIFT 3
-#endif
/* ARM calling convention:
r0-r3, r12: caller-save
/* ARM calling convention:
r0-r3, r12: caller-save
@@
-61,13
+51,10
@@
extern char *invc_ptr;
#define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
// Code generator target address
#define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
// Code generator target address
-#if
def
BASE_ADDR_FIXED
+#if BASE_ADDR_FIXED
// "round" address helpful for debug
#define BASE_ADDR 0x1000000
#else
extern char translation_cache[1 << TARGET_SIZE_2];
// "round" address helpful for debug
#define BASE_ADDR 0x1000000
#else
extern char translation_cache[1 << TARGET_SIZE_2];
-#define BASE_ADDR translation_cache
+#define BASE_ADDR
(u_int)
translation_cache
#endif
#endif
-
-// This is defined in linkage_arm.s, but gcc -O3 likes this better
-#define rdram ((unsigned int *)0x80000000)