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gte_arm: fix gteOF sign extension
[pcsx_rearmed.git]
/
libpcsxcore
/
new_dynarec
/
assem_arm.h
diff --git
a/libpcsxcore/new_dynarec/assem_arm.h
b/libpcsxcore/new_dynarec/assem_arm.h
index
cc8b067
..
7ed8caf
100644
(file)
--- a/
libpcsxcore/new_dynarec/assem_arm.h
+++ b/
libpcsxcore/new_dynarec/assem_arm.h
@@
-8,7
+8,29
@@
#define CORTEX_A8_BRANCH_PREDICTION_HACK 1
#define USE_MINI_HT 1
//#define REG_PREFETCH 1
#define CORTEX_A8_BRANCH_PREDICTION_HACK 1
#define USE_MINI_HT 1
//#define REG_PREFETCH 1
+#define HAVE_CONDITIONAL_CALL 1
#define DISABLE_TLB 1
#define DISABLE_TLB 1
+//#define MUPEN64
+#define FORCE32 1
+#define DISABLE_COP1 1
+#define PCSX 1
+#define RAM_SIZE 0x200000
+
+#ifndef __ARM_ARCH_7A__
+#define ARMv5_ONLY
+//#undef CORTEX_A8_BRANCH_PREDICTION_HACK
+//#undef USE_MINI_HT
+#endif
+
+#ifndef __ANDROID__
+#define BASE_ADDR_FIXED 1
+#endif
+
+#ifdef FORCE32
+#define REG_SHIFT 2
+#else
+#define REG_SHIFT 3
+#endif
/* ARM calling convention:
r0-r3, r12: caller-save
/* ARM calling convention:
r0-r3, r12: caller-save
@@
-36,8
+58,16
@@
extern char *invc_ptr;
extern char *invc_ptr;
-#define BASE_ADDR 0x7000000 // Code generator target address
#define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
#define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
+// Code generator target address
+#ifdef BASE_ADDR_FIXED
+// "round" address helpful for debug
+#define BASE_ADDR 0x1000000
+#else
+extern char translation_cache[1 << TARGET_SIZE_2];
+#define BASE_ADDR translation_cache
+#endif
+
// This is defined in linkage_arm.s, but gcc -O3 likes this better
#define rdram ((unsigned int *)0x80000000)
// This is defined in linkage_arm.s, but gcc -O3 likes this better
#define rdram ((unsigned int *)0x80000000)