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lightrec: Increase size of hw registers area
[pcsx_rearmed.git]
/
libpcsxcore
/
new_dynarec
/
assem_arm.h
diff --git
a/libpcsxcore/new_dynarec/assem_arm.h
b/libpcsxcore/new_dynarec/assem_arm.h
index
7ed8caf
..
b355876
100644
(file)
--- a/
libpcsxcore/new_dynarec/assem_arm.h
+++ b/
libpcsxcore/new_dynarec/assem_arm.h
@@
-1,46
+1,11
@@
-#define HOST_REGS 13
-#define HOST_CCREG 10
-#define HOST_BTREG 8
-#define EXCLUDE_REG 11
-
#define HOST_IMM8 1
#define HAVE_CMOV_IMM 1
#define HOST_IMM8 1
#define HAVE_CMOV_IMM 1
-#define CORTEX_A8_BRANCH_PREDICTION_HACK 1
-#define USE_MINI_HT 1
-//#define REG_PREFETCH 1
#define HAVE_CONDITIONAL_CALL 1
#define HAVE_CONDITIONAL_CALL 1
-#define DISABLE_TLB 1
-//#define MUPEN64
-#define FORCE32 1
-#define DISABLE_COP1 1
-#define PCSX 1
-#define RAM_SIZE 0x200000
-
-#ifndef __ARM_ARCH_7A__
-#define ARMv5_ONLY
-//#undef CORTEX_A8_BRANCH_PREDICTION_HACK
-//#undef USE_MINI_HT
-#endif
-
-#ifndef __ANDROID__
-#define BASE_ADDR_FIXED 1
-#endif
-
-#ifdef FORCE32
-#define REG_SHIFT 2
-#else
-#define REG_SHIFT 3
-#endif
/* ARM calling convention:
r0-r3, r12: caller-save
r4-r11: callee-save */
/* ARM calling convention:
r0-r3, r12: caller-save
r4-r11: callee-save */
-#define ARG1_REG 0
-#define ARG2_REG 1
-#define ARG3_REG 2
-#define ARG4_REG 3
-
/* GCC register naming convention:
r10 = sl (base)
r11 = fp (frame pointer)
/* GCC register naming convention:
r10 = sl (base)
r11 = fp (frame pointer)
@@
-49,25
+14,32
@@
r14 = lr (link register)
r15 = pc (program counter) */
r14 = lr (link register)
r15 = pc (program counter) */
+#define HOST_REGS 13
+#define HOST_CCREG 10
+#define EXCLUDE_REG 11
+
+// Note: FP is set to &dynarec_local when executing generated code.
+// Thus the local variables are actually global and not on the stack.
#define FP 11
#define LR 14
#define HOST_TEMPREG 14
#define FP 11
#define LR 14
#define HOST_TEMPREG 14
-// Note: FP is set to &dynarec_local when executing generated code.
-// Thus the local variables are actually global and not on the stack.
+#ifndef __MACH__
+#define CALLER_SAVE_REGS 0x100f
+#else
+#define CALLER_SAVE_REGS 0x120f
+#endif
+#define PREFERRED_REG_FIRST 4
+#define PREFERRED_REG_LAST 9
+
+#define DRC_DBG_REGMASK CALLER_SAVE_REGS
extern char *invc_ptr;
#define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
extern char *invc_ptr;
#define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
-// Code generator target address
-#ifdef BASE_ADDR_FIXED
-// "round" address helpful for debug
-#define BASE_ADDR 0x1000000
-#else
-extern char translation_cache[1 << TARGET_SIZE_2];
-#define BASE_ADDR translation_cache
-#endif
+struct tramp_insns
+{
+ u_int ldrpc;
+};
-// This is defined in linkage_arm.s, but gcc -O3 likes this better
-#define rdram ((unsigned int *)0x80000000)