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drc: arm64 wip
[pcsx_rearmed.git]
/
libpcsxcore
/
new_dynarec
/
assem_arm.h
diff --git
a/libpcsxcore/new_dynarec/assem_arm.h
b/libpcsxcore/new_dynarec/assem_arm.h
index
2457bb1
..
bbaf5b9
100644
(file)
--- a/
libpcsxcore/new_dynarec/assem_arm.h
+++ b/
libpcsxcore/new_dynarec/assem_arm.h
@@
-8,17
+8,10
@@
#define HAVE_CONDITIONAL_CALL 1
#define RAM_SIZE 0x200000
#define HAVE_CONDITIONAL_CALL 1
#define RAM_SIZE 0x200000
-#define REG_SHIFT 2
-
/* ARM calling convention:
r0-r3, r12: caller-save
r4-r11: callee-save */
/* ARM calling convention:
r0-r3, r12: caller-save
r4-r11: callee-save */
-#define ARG1_REG 0
-#define ARG2_REG 1
-#define ARG3_REG 2
-#define ARG4_REG 3
-
/* GCC register naming convention:
r10 = sl (base)
r11 = fp (frame pointer)
/* GCC register naming convention:
r10 = sl (base)
r11 = fp (frame pointer)