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(Vita) Have to set DRC_CACHE_BASE to 0 for now
[pcsx_rearmed.git]
/
libpcsxcore
/
new_dynarec
/
assem_arm.h
diff --git
a/libpcsxcore/new_dynarec/assem_arm.h
b/libpcsxcore/new_dynarec/assem_arm.h
index
0148a95
..
da4144d
100644
(file)
--- a/
libpcsxcore/new_dynarec/assem_arm.h
+++ b/
libpcsxcore/new_dynarec/assem_arm.h
@@
-17,18
+17,13
@@
#define RAM_SIZE 0x200000
#ifndef __ARM_ARCH_7A__
#define RAM_SIZE 0x200000
#ifndef __ARM_ARCH_7A__
-#define ARMv5_ONLY
//#undef CORTEX_A8_BRANCH_PREDICTION_HACK
//#undef USE_MINI_HT
#endif
#ifndef BASE_ADDR_FIXED
//#undef CORTEX_A8_BRANCH_PREDICTION_HACK
//#undef USE_MINI_HT
#endif
#ifndef BASE_ADDR_FIXED
-#ifndef __ANDROID__
-#define BASE_ADDR_FIXED 1
-#else
#define BASE_ADDR_FIXED 0
#endif
#define BASE_ADDR_FIXED 0
#endif
-#endif
#ifdef FORCE32
#define REG_SHIFT 2
#ifdef FORCE32
#define REG_SHIFT 2
@@
-69,6
+64,10
@@
extern char *invc_ptr;
// "round" address helpful for debug
#define BASE_ADDR 0x1000000
#else
// "round" address helpful for debug
#define BASE_ADDR 0x1000000
#else
+#if defined(VITA)
+extern char* translation_cache;
+#else
extern char translation_cache[1 << TARGET_SIZE_2];
extern char translation_cache[1 << TARGET_SIZE_2];
-#define BASE_ADDR translation_cache
+#endif
+#define BASE_ADDR (u_int)translation_cache
#endif
#endif