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fix some more 32/64bit incompatibilities
[pcsx_rearmed.git]
/
libpcsxcore
/
new_dynarec
/
assem_arm.h
diff --git
a/libpcsxcore/new_dynarec/assem_arm.h
b/libpcsxcore/new_dynarec/assem_arm.h
index
7ed8caf
..
f4e36a9
100644
(file)
--- a/
libpcsxcore/new_dynarec/assem_arm.h
+++ b/
libpcsxcore/new_dynarec/assem_arm.h
@@
-22,8
+22,8
@@
//#undef USE_MINI_HT
#endif
//#undef USE_MINI_HT
#endif
-#ifndef
__ANDROID__
-#define BASE_ADDR_FIXED
1
+#ifndef
BASE_ADDR_FIXED
+#define BASE_ADDR_FIXED
0
#endif
#ifdef FORCE32
#endif
#ifdef FORCE32
@@
-61,13
+61,10
@@
extern char *invc_ptr;
#define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
// Code generator target address
#define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
// Code generator target address
-#if
def
BASE_ADDR_FIXED
+#if BASE_ADDR_FIXED
// "round" address helpful for debug
#define BASE_ADDR 0x1000000
#else
extern char translation_cache[1 << TARGET_SIZE_2];
// "round" address helpful for debug
#define BASE_ADDR 0x1000000
#else
extern char translation_cache[1 << TARGET_SIZE_2];
-#define BASE_ADDR translation_cache
+#define BASE_ADDR
(u_int)
translation_cache
#endif
#endif
-
-// This is defined in linkage_arm.s, but gcc -O3 likes this better
-#define rdram ((unsigned int *)0x80000000)