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dfxvideo: Restore support for big-endian arch
[pcsx_rearmed.git]
/
libpcsxcore
/
new_dynarec
/
assem_arm64.c
diff --git
a/libpcsxcore/new_dynarec/assem_arm64.c
b/libpcsxcore/new_dynarec/assem_arm64.c
index
3a88f9e
..
b2b8110
100644
(file)
--- a/
libpcsxcore/new_dynarec/assem_arm64.c
+++ b/
libpcsxcore/new_dynarec/assem_arm64.c
@@
-31,7
+31,7
@@
void do_memhandler_post();
/* Linker */
static void set_jump_target(void *addr, void *target)
{
/* Linker */
static void set_jump_target(void *addr, void *target)
{
- u_int *ptr =
addr
;
+ u_int *ptr =
NDRC_WRITE_OFFSET(addr)
;
intptr_t offset = (u_char *)target - (u_char *)addr;
if ((*ptr&0xFC000000) == 0x14000000) { // b
intptr_t offset = (u_char *)target - (u_char *)addr;
if ((*ptr&0xFC000000) == 0x14000000) { // b
@@
-142,7
+142,7
@@
static unused const char *condname[16] = {
static void output_w32(u_int word)
{
static void output_w32(u_int word)
{
- *((u_int *)
out
) = word;
+ *((u_int *)
NDRC_WRITE_OFFSET(out)
) = word;
out += 4;
}
out += 4;
}
@@
-838,6
+838,12
@@
static void emit_cmp(u_int rs,u_int rt)
output_w32(0x6b000000 | rm_rn_rd(rt, rs, WZR));
}
output_w32(0x6b000000 | rm_rn_rd(rt, rs, WZR));
}
+static void emit_cmpcs(u_int rs,u_int rt)
+{
+ assem_debug("ccmp %s,%s,#0,cs\n",regname[rs],regname[rt]);
+ output_w32(0x7a400000 | (COND_CS << 12) | rm_rn_rd(rt, rs, 0));
+}
+
static void emit_set_gz32(u_int rs, u_int rt)
{
//assem_debug("set_gz32\n");
static void emit_set_gz32(u_int rs, u_int rt)
{
//assem_debug("set_gz32\n");
@@
-1892,7
+1898,7
@@
static void do_miniht_insert(u_int return_address,u_int rt,int temp) {
emit_writeword(rt,&mini_ht[(return_address&0xFF)>>3][0]);
}
emit_writeword(rt,&mini_ht[(return_address&0xFF)>>3][0]);
}
-static void clear_cache_arm64(char *start, char *end)
+static
unused
void clear_cache_arm64(char *start, char *end)
{
// Don't rely on GCC's __clear_cache implementation, as it caches
// icache/dcache cache line sizes, that can vary between cores on
{
// Don't rely on GCC's __clear_cache implementation, as it caches
// icache/dcache cache line sizes, that can vary between cores on
@@
-1937,7
+1943,7
@@
static void clear_cache_arm64(char *start, char *end)
static void arch_init(void)
{
uintptr_t diff = (u_char *)&ndrc->tramp.f - (u_char *)&ndrc->tramp.ops;
static void arch_init(void)
{
uintptr_t diff = (u_char *)&ndrc->tramp.f - (u_char *)&ndrc->tramp.ops;
- struct tramp_insns *ops =
ndrc->tramp.ops
;
+ struct tramp_insns *ops =
NDRC_WRITE_OFFSET(ndrc->tramp.ops)
;
size_t i;
assert(!(diff & 3));
start_tcache_write(ops, (u_char *)ops + sizeof(ndrc->tramp.ops));
size_t i;
assert(!(diff & 3));
start_tcache_write(ops, (u_char *)ops + sizeof(ndrc->tramp.ops));