+
+#else // if DRC_DISABLE
+
+unsigned int address;
+int pending_exception, stop;
+unsigned int next_interupt;
+int new_dynarec_did_compile;
+int cycle_multiplier;
+int cycle_multiplier_override;
+int new_dynarec_hacks_pergame;
+int new_dynarec_hacks;
+void *psxH_ptr;
+void *zeromem_ptr;
+u8 zero_mem[0x1000];
+unsigned char *out;
+void *mem_rtab;
+void *scratch_buf_ptr;
+void new_dynarec_init() {}
+void new_dyna_start(void *context) {}
+void new_dynarec_cleanup() {}
+void new_dynarec_clear_full() {}
+void invalidate_all_pages() {}
+void invalidate_block(unsigned int block) {}
+void new_dyna_pcsx_mem_init(void) {}
+void new_dyna_pcsx_mem_reset(void) {}
+void new_dyna_pcsx_mem_load_state(void) {}
+void new_dyna_pcsx_mem_shutdown(void) {}
+int new_dynarec_save_blocks(void *save, int size) { return 0; }
+void new_dynarec_load_blocks(const void *save, int size) {}
+#endif
+
+#ifdef DRC_DBG
+
+#include <stddef.h>
+static FILE *f;
+extern u32 last_io_addr;
+
+static void dump_mem(const char *fname, void *mem, size_t size)
+{
+ FILE *f1 = fopen(fname, "wb");
+ if (f1 == NULL)
+ f1 = fopen(strrchr(fname, '/') + 1, "wb");
+ fwrite(mem, 1, size, f1);
+ fclose(f1);
+}
+
+static u32 memcheck_read(u32 a)
+{
+ if ((a >> 16) == 0x1f80)
+ // scratchpad/IO
+ return *(u32 *)(psxH + (a & 0xfffc));
+
+ if ((a >> 16) == 0x1f00)
+ // parallel
+ return *(u32 *)(psxP + (a & 0xfffc));
+
+// if ((a & ~0xe0600000) < 0x200000)
+ // RAM
+ return *(u32 *)(psxM + (a & 0x1ffffc));
+}
+
+#if 0
+void do_insn_trace(void)
+{
+ static psxRegisters oldregs;
+ static u32 old_io_addr = (u32)-1;
+ static u32 old_io_data = 0xbad0c0de;
+ static u32 event_cycles_o[PSXINT_COUNT];
+ u32 *allregs_p = (void *)&psxRegs;
+ u32 *allregs_o = (void *)&oldregs;
+ u32 io_data;
+ int i;
+ u8 byte;
+
+ //last_io_addr = 0x5e2c8;
+ if (f == NULL)
+ f = fopen("tracelog", "wb");
+
+ // log reg changes
+ oldregs.code = psxRegs.code; // don't care
+ for (i = 0; i < offsetof(psxRegisters, intCycle) / 4; i++) {
+ if (allregs_p[i] != allregs_o[i]) {
+ fwrite(&i, 1, 1, f);
+ fwrite(&allregs_p[i], 1, 4, f);
+ allregs_o[i] = allregs_p[i];
+ }
+ }
+ // log event changes
+ for (i = 0; i < PSXINT_COUNT; i++) {
+ if (event_cycles[i] != event_cycles_o[i]) {
+ byte = 0xfc;
+ fwrite(&byte, 1, 1, f);
+ fwrite(&i, 1, 1, f);
+ fwrite(&event_cycles[i], 1, 4, f);
+ event_cycles_o[i] = event_cycles[i];
+ }
+ }
+ // log last io
+ if (old_io_addr != last_io_addr) {
+ byte = 0xfd;
+ fwrite(&byte, 1, 1, f);
+ fwrite(&last_io_addr, 1, 4, f);
+ old_io_addr = last_io_addr;
+ }
+ io_data = memcheck_read(last_io_addr);
+ if (old_io_data != io_data) {
+ byte = 0xfe;
+ fwrite(&byte, 1, 1, f);
+ fwrite(&io_data, 1, 4, f);
+ old_io_data = io_data;
+ }
+ byte = 0xff;
+ fwrite(&byte, 1, 1, f);
+
+#if 0
+ if (psxRegs.cycle == 190230) {
+ dump_mem("/mnt/ntz/dev/pnd/tmp/psxram_i.dump", psxM, 0x200000);
+ dump_mem("/mnt/ntz/dev/pnd/tmp/psxregs_i.dump", psxH, 0x10000);
+ printf("dumped\n");
+ exit(1);
+ }
+#endif
+}
+#endif
+
+static const char *regnames[offsetof(psxRegisters, intCycle) / 4] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+ "lo", "hi",
+ "C0_0", "C0_1", "C0_2", "C0_3", "C0_4", "C0_5", "C0_6", "C0_7",
+ "C0_8", "C0_9", "C0_10", "C0_11", "C0_12", "C0_13", "C0_14", "C0_15",
+ "C0_16", "C0_17", "C0_18", "C0_19", "C0_20", "C0_21", "C0_22", "C0_23",
+ "C0_24", "C0_25", "C0_26", "C0_27", "C0_28", "C0_29", "C0_30", "C0_31",
+
+ "C2D0", "C2D1", "C2D2", "C2D3", "C2D4", "C2D5", "C2D6", "C2D7",
+ "C2D8", "C2D9", "C2D10", "C2D11", "C2D12", "C2D13", "C2D14", "C2D15",
+ "C2D16", "C2D17", "C2D18", "C2D19", "C2D20", "C2D21", "C2D22", "C2D23",
+ "C2D24", "C2D25", "C2D26", "C2D27", "C2D28", "C2D29", "C2D30", "C2D31",
+
+ "C2C0", "C2C1", "C2C2", "C2C3", "C2C4", "C2C5", "C2C6", "C2C7",
+ "C2C8", "C2C9", "C2C10", "C2C11", "C2C12", "C2C13", "C2C14", "C2C15",
+ "C2C16", "C2C17", "C2C18", "C2C19", "C2C20", "C2C21", "C2C22", "C2C23",
+ "C2C24", "C2C25", "C2C26", "C2C27", "C2C28", "C2C29", "C2C30", "C2C31",
+
+ "PC", "code", "cycle", "interrupt",
+};
+
+static struct {
+ int reg;
+ u32 val, val_expect;
+ u32 pc, cycle;
+} miss_log[64];
+static int miss_log_i;
+#define miss_log_len (sizeof(miss_log)/sizeof(miss_log[0]))
+#define miss_log_mask (miss_log_len-1)
+
+static void miss_log_add(int reg, u32 val, u32 val_expect, u32 pc, u32 cycle)
+{
+ miss_log[miss_log_i].reg = reg;
+ miss_log[miss_log_i].val = val;
+ miss_log[miss_log_i].val_expect = val_expect;
+ miss_log[miss_log_i].pc = pc;
+ miss_log[miss_log_i].cycle = cycle;
+ miss_log_i = (miss_log_i + 1) & miss_log_mask;
+}
+
+void breakme() {}
+
+void do_insn_cmp(void)
+{
+ static psxRegisters rregs;
+ static u32 mem_addr, mem_val;
+ u32 *allregs_p = (void *)&psxRegs;
+ u32 *allregs_e = (void *)&rregs;
+ static u32 ppc, failcount;
+ int i, ret, bad = 0, which_event = -1;
+ u32 ev_cycles = 0;
+ u8 code;
+
+ if (f == NULL)
+ f = fopen("tracelog", "rb");
+
+ while (1) {
+ if ((ret = fread(&code, 1, 1, f)) <= 0)
+ break;
+ if (ret <= 0)
+ break;
+ if (code == 0xff)
+ break;
+ switch (code) {
+ case 0xfc:
+ which_event = 0;
+ fread(&which_event, 1, 1, f);
+ fread(&ev_cycles, 1, 4, f);
+ continue;
+ case 0xfd:
+ fread(&mem_addr, 1, 4, f);
+ continue;
+ case 0xfe:
+ fread(&mem_val, 1, 4, f);
+ continue;
+ }
+ fread(&allregs_e[code], 1, 4, f);
+ }
+
+ if (ret <= 0) {
+ printf("EOF?\n");
+ goto end;
+ }
+
+ psxRegs.code = rregs.code; // don't care
+ psxRegs.cycle = rregs.cycle;
+ psxRegs.CP0.r[9] = rregs.CP0.r[9]; // Count
+
+ //if (psxRegs.cycle == 166172) breakme();
+
+ if (memcmp(&psxRegs, &rregs, offsetof(psxRegisters, intCycle)) == 0 &&
+ mem_val == memcheck_read(mem_addr)
+ ) {
+ failcount = 0;
+ goto ok;
+ }
+
+ for (i = 0; i < offsetof(psxRegisters, intCycle) / 4; i++) {
+ if (allregs_p[i] != allregs_e[i]) {
+ miss_log_add(i, allregs_p[i], allregs_e[i], psxRegs.pc, psxRegs.cycle);
+ bad++;
+ if (i > 32+2)
+ goto end;
+ }
+ }
+
+ if (mem_val != memcheck_read(mem_addr)) {
+ printf("bad mem @%08x: %08x %08x\n", mem_addr, memcheck_read(mem_addr), mem_val);
+ goto end;
+ }
+
+ if (which_event >= 0 && event_cycles[which_event] != ev_cycles) {
+ printf("bad ev_cycles #%d: %08x %08x\n", which_event, event_cycles[which_event], ev_cycles);
+ goto end;
+ }
+
+ if (psxRegs.pc == rregs.pc && bad < 6 && failcount < 32) {
+ static int last_mcycle;
+ if (last_mcycle != psxRegs.cycle >> 20) {
+ printf("%u\n", psxRegs.cycle);
+ last_mcycle = psxRegs.cycle >> 20;
+ }
+ failcount++;
+ goto ok;
+ }
+
+end:
+ for (i = 0; i < miss_log_len; i++, miss_log_i = (miss_log_i + 1) & miss_log_mask)
+ printf("bad %5s: %08x %08x, pc=%08x, cycle %u\n",
+ regnames[miss_log[miss_log_i].reg], miss_log[miss_log_i].val,
+ miss_log[miss_log_i].val_expect, miss_log[miss_log_i].pc, miss_log[miss_log_i].cycle);
+ printf("-- %d\n", bad);
+ for (i = 0; i < 8; i++)
+ printf("r%d=%08x r%2d=%08x r%2d=%08x r%2d=%08x\n", i, allregs_p[i],
+ i+8, allregs_p[i+8], i+16, allregs_p[i+16], i+24, allregs_p[i+24]);
+ printf("PC: %08x/%08x, cycle %u\n", psxRegs.pc, ppc, psxRegs.cycle);
+ dump_mem("/mnt/ntz/dev/pnd/tmp/psxram.dump", psxM, 0x200000);
+ dump_mem("/mnt/ntz/dev/pnd/tmp/psxregs.dump", psxH, 0x10000);
+ exit(1);
+ok:
+ psxRegs.cycle = rregs.cycle + 2; // sync timing
+ ppc = psxRegs.pc;
+}
+
+#endif