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dma: change timing back to 1.92 levels
[pcsx_rearmed.git]
/
libpcsxcore
/
new_dynarec
/
emu_if.c
diff --git
a/libpcsxcore/new_dynarec/emu_if.c
b/libpcsxcore/new_dynarec/emu_if.c
index
9b16537
..
3bfec4e
100644
(file)
--- a/
libpcsxcore/new_dynarec/emu_if.c
+++ b/
libpcsxcore/new_dynarec/emu_if.c
@@
-61,6
+61,9
@@
static irq_func * const irq_funcs[] = {
[PSXINT_SPUDMA] = spuInterrupt,
[PSXINT_MDECINDMA] = mdec0Interrupt,
[PSXINT_GPUOTCDMA] = gpuotcInterrupt,
[PSXINT_SPUDMA] = spuInterrupt,
[PSXINT_MDECINDMA] = mdec0Interrupt,
[PSXINT_GPUOTCDMA] = gpuotcInterrupt,
+ [PSXINT_CDRDMA] = cdrDmaInterrupt,
+ [PSXINT_CDRLID] = cdrLidSeekInterrupt,
+ [PSXINT_CDRPLAY] = cdrPlayInterrupt,
};
/* local dupe of psxBranchTest, using event_cycles */
};
/* local dupe of psxBranchTest, using event_cycles */
@@
-109,19
+112,20
@@
void gen_interupt()
next_interupt, next_interupt - psxRegs.cycle);
}
next_interupt, next_interupt - psxRegs.cycle);
}
-void MTC0_()
-{
- extern void psxMTC0();
+// from interpreter
+extern void MTC0(int reg, u32 val);
- evprintf("ari64 MTC0 %08x %08x %u\n", psxRegs.code, psxRegs.pc, psxRegs.cycle);
- psxMTC0();
- gen_interupt(); /* FIXME: checking pending irqs should be enough */
+void pcsx_mtc0(u32 reg)
+{
+ evprintf("MTC0 %d #%x @%08x %u\n", reg, readmem_word, psxRegs.pc, psxRegs.cycle);
+ MTC0(reg, readmem_word);
+ gen_interupt();
}
}
-void
check_interupt(
)
+void
pcsx_mtc0_ds(u32 reg
)
{
{
- /* FIXME (also asm) */
-
printf("ari64_check_interupt\n"
);
+ evprintf("MTC0 %d #%x @%08x %u\n", reg, readmem_word, psxRegs.pc, psxRegs.cycle);
+
MTC0(reg, readmem_word
);
}
void new_dyna_save(void)
}
void new_dyna_save(void)
@@
-132,7
+136,7
@@
void new_dyna_save(void)
void new_dyna_restore(void)
{
int i;
void new_dyna_restore(void)
{
int i;
- for (i = 0; i < PSXINT_
NEWDRC_CHECK
; i++)
+ for (i = 0; i < PSXINT_
COUNT
; i++)
event_cycles[i] = psxRegs.intCycle[i].sCycle + psxRegs.intCycle[i].cycle;
}
event_cycles[i] = psxRegs.intCycle[i].sCycle + psxRegs.intCycle[i].cycle;
}
@@
-171,10
+175,13
@@
static void ari64_reset()
printf("ari64_reset\n");
new_dyna_pcsx_mem_reset();
invalidate_all_pages();
printf("ari64_reset\n");
new_dyna_pcsx_mem_reset();
invalidate_all_pages();
+ new_dyna_restore();
pending_exception = 1;
}
pending_exception = 1;
}
-static void ari64_execute()
+// execute until predefined leave points
+// (HLE softcall exit and BIOS fastboot end)
+static void ari64_execute_until()
{
schedule_timeslice();
{
schedule_timeslice();
@@
-187,23
+194,30
@@
static void ari64_execute()
psxRegs.cycle, next_interupt, next_interupt - psxRegs.cycle);
}
psxRegs.cycle, next_interupt, next_interupt - psxRegs.cycle);
}
+static void ari64_execute()
+{
+ while (!stop) {
+ ari64_execute_until();
+ evprintf("drc left @%08x\n", psxRegs.pc);
+ }
+}
+
static void ari64_clear(u32 addr, u32 size)
{
static void ari64_clear(u32 addr, u32 size)
{
- u32 start, end;
+ u32 start, end, main_ram;
+
+ size *= 4; /* PCSX uses DMA units */
evprintf("ari64_clear %08x %04x\n", addr, size);
/* check for RAM mirrors */
evprintf("ari64_clear %08x %04x\n", addr, size);
/* check for RAM mirrors */
- if ((addr & ~0xe0600000) < 0x200000) {
- addr &= ~0xe0600000;
- addr |= 0x80000000;
- }
+ main_ram = (addr & 0xffe00000) == 0x80000000;
start = addr >> 12;
end = (addr + size) >> 12;
for (; start <= end; start++)
start = addr >> 12;
end = (addr + size) >> 12;
for (; start <= end; start++)
- if (!invalid_code[start])
+ if (!
main_ram || !
invalid_code[start])
invalidate_block(start);
}
invalidate_block(start);
}
@@
-226,7
+240,7
@@
R3000Acpu psxRec = {
ari64_reset,
#if defined(__arm__)
ari64_execute,
ari64_reset,
#if defined(__arm__)
ari64_execute,
- ari64_execute,
+ ari64_execute
_until
,
#else
intExecuteT,
intExecuteBlockT,
#else
intExecuteT,
intExecuteBlockT,