+.endm
+
+ari_read_ram_mirror8:
+ ari_read_ram_mirror 0, ldrb
+
+ari_read_ram_mirror16:
+ ari_read_ram_mirror (1<<11), ldrh
+
+ari_read_ram_mirror32:
+ ari_read_ram_mirror (3<<11), ldr
+
+/* invalidation is already taken care of by the caller */
+.macro ari_write_ram bic_const var pf
+ ldr r0, [fp, #address-dynarec_local]
+ ldr\pf r1, [fp, #\var-dynarec_local]
+.if \bic_const
+ bic r0, r0, #\bic_const
+.endif
+ str\pf r1, [r0]
+ mov pc, lr
+.endm
+
+ari_write_ram8:
+ ari_write_ram 0, byte, b
+
+ari_write_ram16:
+ ari_write_ram 1, hword, h
+
+ari_write_ram32:
+ ari_write_ram 3, word,
+
+.macro ari_write_ram_mirror mvn_const var pf
+ ldr r0, [fp, #address-dynarec_local]
+ mvn r3, #\mvn_const
+ ldr\pf r1, [fp, #\var-dynarec_local]
+ and r0, r3, lsr #11
+ ldr r2, [fp, #invc_ptr-dynarec_local]
+ orr r0, r0, #1<<31
+ ldrb r2, [r2, r0, lsr #12]
+ str\pf r1, [r0]
+ tst r2, r2
+ movne pc, lr
+ ldr r1, [fp, #inv_code_start-dynarec_local]
+ ldr r2, [fp, #inv_code_end-dynarec_local]
+ cmp r0, r1
+ cmpcs r2, r0
+ movcs pc, lr
+ nop
+ b invalidate_addr
+.endm
+
+ari_write_ram_mirror8:
+ ari_write_ram_mirror 0, byte, b
+
+ari_write_ram_mirror16:
+ ari_write_ram_mirror (1<<11), hword, h
+
+ari_write_ram_mirror32:
+ ari_write_ram_mirror (3<<11), word,
+
+ari_write_ram_mirror_ro32:
+ load_var_adr r0, pcsx_ram_is_ro
+ ldr r0, [r0]
+ tst r0, r0
+ movne pc, lr
+ nop
+ b ari_write_ram_mirror32
+
+
+.macro ari_read_bios_mirror bic_const op
+ ldr r0, [fp, #address-dynarec_local]
+ orr r0, r0, #0x80000000
+ bic r0, r0, #(0x20000000|\bic_const) @ map to 0x9fc...
+ \op r0, [r0]
+ str r0, [fp, #readmem_dword-dynarec_local]
+ mov pc, lr
+.endm
+
+ari_read_bios8:
+ ari_read_bios_mirror 0, ldrb
+
+ari_read_bios16:
+ ari_read_bios_mirror 1, ldrh
+
+ari_read_bios32:
+ ari_read_bios_mirror 3, ldr
+
+
+@ for testing
+.macro ari_read_io_old tab_shift
+ str lr, [sp, #-8]! @ EABI alignment..
+.if \tab_shift == 0
+ bl psxHwRead32
+.endif
+.if \tab_shift == 1
+ bl psxHwRead16
+.endif
+.if \tab_shift == 2
+ bl psxHwRead8
+.endif
+ str r0, [fp, #readmem_dword-dynarec_local]
+ ldr pc, [sp], #8
+.endm
+
+.macro ari_read_io readop mem_tab tab_shift
+ ldr r0, [fp, #address-dynarec_local]
+ ldr r1, [fp, #psxH_ptr-dynarec_local]
+.if \tab_shift == 0
+ bic r0, r0, #3
+.endif
+.if \tab_shift == 1
+ bic r0, r0, #1
+.endif
+ bic r2, r0, #0x1f800000
+ ldr r12,[fp, #\mem_tab-dynarec_local]
+ subs r3, r2, #0x1000
+ blo 2f
+@ ari_read_io_old \tab_shift
+ cmp r3, #0x880
+ bhs 1f
+ ldr r12,[r12, r3, lsl #\tab_shift]
+ tst r12,r12
+ beq 2f
+0:
+ str lr, [sp, #-8]! @ EABI alignment..
+ blx r12
+ str r0, [fp, #readmem_dword-dynarec_local]
+ ldr pc, [sp], #8
+
+1:
+.if \tab_shift == 1 @ read16
+ cmp r2, #0x1c00
+ blo 2f
+ cmp r2, #0x1e00
+ bhs 2f
+ ldr r12,[fp, #spu_readf-dynarec_local]
+ b 0b
+.endif
+2:
+ @ no handler, just read psxH
+ \readop r0, [r1, r2]
+ str r0, [fp, #readmem_dword-dynarec_local]
+ mov pc, lr
+.endm
+
+ari_read_io8:
+ ari_read_io ldrb, tab_read8, 2
+
+ari_read_io16:
+ ari_read_io ldrh, tab_read16, 1
+
+ari_read_io32:
+ ari_read_io ldr, tab_read32, 0
+
+.macro ari_write_io_old tab_shift
+.if \tab_shift == 0
+ b psxHwWrite32
+.endif
+.if \tab_shift == 1
+ b psxHwWrite16
+.endif
+.if \tab_shift == 2
+ b psxHwWrite8
+.endif
+.endm
+
+.macro ari_write_io pf var mem_tab tab_shift
+ ldr r0, [fp, #address-dynarec_local]
+ ldr\pf r1, [fp, #\var-dynarec_local]
+.if \tab_shift == 0
+ bic r0, r0, #3
+.endif
+.if \tab_shift == 1
+ bic r0, r0, #1
+.endif
+ bic r2, r0, #0x1f800000
+ ldr r12,[fp, #\mem_tab-dynarec_local]
+ subs r3, r2, #0x1000
+ blo 0f
+@ ari_write_io_old \tab_shift
+ cmp r3, #0x880
+ bhs 1f
+ ldr r12,[r12, r3, lsl #\tab_shift]
+ mov r0, r1
+ tst r12,r12
+ bxne r12
+0:
+ ldr r3, [fp, #psxH_ptr-dynarec_local]
+ str\pf r1, [r2, r3]
+ mov pc, lr
+1:
+ cmp r2, #0x1c00
+ blo 0b
+ cmp r2, #0x1e00
+.if \tab_shift != 0
+ ldrlo pc, [fp, #spu_writef-dynarec_local]
+.else
+ @ write32 to SPU - very rare case (is this correct?)
+ bhs 0b
+ add r2, r0, #2
+ mov r3, r1, lsr #16
+ push {r2,r3,lr}
+ mov lr, pc
+ ldr pc, [fp, #spu_writef-dynarec_local]
+ pop {r0,r1,lr}
+ ldr pc, [fp, #spu_writef-dynarec_local]
+.endif
+ nop
+ b 0b
+.endm
+
+ari_write_io8:
+ @ PCSX always writes to psxH, so do we for consistency
+ ldr r0, [fp, #address-dynarec_local]
+ ldr r3, [fp, #psxH_ptr-dynarec_local]
+ ldrb r1, [fp, #byte-dynarec_local]
+ bic r2, r0, #0x1f800000
+ ldr r12,[fp, #tab_write8-dynarec_local]
+ strb r1, [r2, r3]
+ subs r3, r2, #0x1000
+ movlo pc, lr
+@ ari_write_io_old 2
+ cmp r3, #0x880
+ movhs pc, lr
+ ldr r12,[r12, r3, lsl #2]
+ mov r0, r1
+ tst r12,r12
+ bxne r12
+ mov pc, lr
+
+ari_write_io16:
+ ari_write_io h, hword, tab_write16, 1
+
+ari_write_io32:
+ ari_write_io , word, tab_write32, 0
+
+/* */
+
+.macro pcsx_read_mem readop tab_shift
+ /* r0 = address, r1 = handler_tab, r2 = cycles */
+ lsl r3, r0, #20
+ lsr r3, #(20+\tab_shift)
+ ldr r12, [fp, #last_count-dynarec_local]
+ ldr r1, [r1, r3, lsl #2]
+ add r2, r2, r12
+ lsls r1, #1
+.if \tab_shift == 1
+ lsl r3, #1
+ \readop r0, [r1, r3]
+.else
+ \readop r0, [r1, r3, lsl #\tab_shift]
+.endif
+ movcc pc, lr
+ str r2, [fp, #cycle-dynarec_local]
+ bx r1
+.endm
+
+jump_handler_read8:
+ add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
+ pcsx_read_mem ldrccb, 0
+
+jump_handler_read16:
+ add r1, #0x1000/4*4 @ shift to r16 part
+ pcsx_read_mem ldrcch, 1
+
+jump_handler_read32:
+ pcsx_read_mem ldrcc, 2
+
+
+.macro pcsx_write_mem wrtop tab_shift
+ /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
+ lsl r12,r0, #20
+ lsr r12, #(20+\tab_shift)
+ ldr r3, [r3, r12, lsl #2]
+ str r0, [fp, #address-dynarec_local] @ some handlers still need it..
+ lsls r3, #1
+ mov r0, r2 @ cycle return in case of direct store
+.if \tab_shift == 1
+ lsl r12, #1
+ \wrtop r1, [r3, r12]
+.else
+ \wrtop r1, [r3, r12, lsl #\tab_shift]
+.endif
+ movcc pc, lr
+ ldr r12, [fp, #last_count-dynarec_local]
+ mov r0, r1
+ add r2, r2, r12
+ push {r2, lr}
+ str r2, [fp, #cycle-dynarec_local]
+ blx r3
+
+ ldr r0, [fp, #next_interupt-dynarec_local]
+ pop {r2, r3}
+ str r0, [fp, #last_count-dynarec_local]
+ sub r0, r2, r0
+ bx r3
+.endm
+
+jump_handler_write8:
+ add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
+ pcsx_write_mem strccb, 0
+
+jump_handler_write16:
+ add r3, #0x1000/4*4 @ shift to r16 part
+ pcsx_write_mem strcch, 1
+
+jump_handler_write32:
+ pcsx_write_mem strcc, 2
+
+jump_handler_write_h:
+ /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
+ ldr r12, [fp, #last_count-dynarec_local]
+ str r0, [fp, #address-dynarec_local] @ some handlers still need it..
+ add r2, r2, r12
+ mov r0, r1
+ push {r2, lr}
+ str r2, [fp, #cycle-dynarec_local]
+ blx r3
+
+ ldr r0, [fp, #next_interupt-dynarec_local]
+ pop {r2, r3}
+ str r0, [fp, #last_count-dynarec_local]
+ sub r0, r2, r0
+ bx r3
+
+jump_handle_swl:
+ /* r0 = address, r1 = data, r2 = cycles */
+ ldr r3, [fp, #mem_wtab-dynarec_local]
+ mov r12,r0,lsr #12
+ ldr r3, [r3, r12, lsl #2]
+ lsls r3, #1
+ bcs 4f
+ add r3, r0, r3
+ mov r0, r2
+ tst r3, #2
+ beq 101f
+ tst r3, #1
+ beq 2f
+3:
+ str r1, [r3, #-3]
+ bx lr
+2:
+ lsr r2, r1, #8
+ lsr r1, #24
+ strh r2, [r3, #-2]
+ strb r1, [r3]
+ bx lr
+101:
+ tst r3, #1
+ lsrne r1, #16 @ 1
+ lsreq r12, r1, #24 @ 0
+ strneh r1, [r3, #-1]
+ streqb r12, [r3]
+ bx lr
+4:
+ mov r0, r2
+ b abort
+ bx lr @ TODO?
+
+
+jump_handle_swr:
+ /* r0 = address, r1 = data, r2 = cycles */
+ ldr r3, [fp, #mem_wtab-dynarec_local]
+ mov r12,r0,lsr #12
+ ldr r3, [r3, r12, lsl #2]
+ lsls r3, #1
+ bcs 4f
+ add r3, r0, r3
+ and r12,r3, #3
+ mov r0, r2
+ cmp r12,#2
+ strgtb r1, [r3] @ 3
+ streqh r1, [r3] @ 2
+ cmp r12,#1
+ strlt r1, [r3] @ 0
+ bxne lr
+ lsr r2, r1, #8 @ 1
+ strb r1, [r3]
+ strh r2, [r3, #1]
+ bx lr
+4:
+ mov r0, r2
+ b abort
+ bx lr @ TODO?
+
+
+@ vim:filetype=armasm