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drc: do MVMVA decoding; parametrize handlers
[pcsx_rearmed.git]
/
libpcsxcore
/
new_dynarec
/
new_dynarec.c
diff --git
a/libpcsxcore/new_dynarec/new_dynarec.c
b/libpcsxcore/new_dynarec/new_dynarec.c
index
9698037
..
e2c63ed
100644
(file)
--- a/
libpcsxcore/new_dynarec/new_dynarec.c
+++ b/
libpcsxcore/new_dynarec/new_dynarec.c
@@
-8651,8
+8651,9
@@
int new_recompile_block(int addr)
rs2[i]=0;
rt1[i]=0;
rt2[i]=0;
rs2[i]=0;
rt1[i]=0;
rt2[i]=0;
- gte_rt[i]=1ll<<63; // every op changes flags
- // TODO: other regs?
+ gte_rs[i]=gte_reg_reads[source[i]&0x3f];
+ gte_rt[i]=gte_reg_writes[source[i]&0x3f];
+ gte_rt[i]|=1ll<<63; // every op changes flags
break;
case FLOAT:
case FCONV:
break;
case FLOAT:
case FCONV:
@@
-9735,6
+9736,11
@@
int new_recompile_block(int addr)
cc=0;
}
#ifdef PCSX
cc=0;
}
#ifdef PCSX
+ else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
+ {
+ // GTE runs in parallel until accessed, divide by 2 for a rough guess
+ cc+=gte_cycletab[source[i]&0x3f]/2;
+ }
else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
{
cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
{
cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)