-+#define doBranchNotTaken() do { psxRegs.cycle += BIAS; execI(); psxBranchTest(); psxRegs.cycle -= BIAS; } while(0)
- /*********************************************************
- * Register branch logic *
- * Format: OP rs, offset *
- *********************************************************/
--#define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_);
--#define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } }
-+#define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); else doBranchNotTaken();
-+#define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } else doBranchNotTaken(); }
-
- void psxBGEZ() { RepZBranchi32(>=) } // Branch if Rs >= 0
- void psxBGEZAL() { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link
-@@ -702,7 +707,7 @@ void psxRFE() {
- * Register branch logic *
- * Format: OP rs, rt, offset *
- *********************************************************/
--#define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_);
-+#define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_); else doBranchNotTaken();
-
- void psxBEQ() { RepBranchi32(==) } // Branch if Rs == Rt
- void psxBNE() { RepBranchi32(!=) } // Branch if Rs != Rt
-@@ -886,6 +891,7 @@ void MTC0(int reg, u32 val) {
- case 12: // Status
- psxRegs.CP0.r[12] = val;
- psxTestSWInts();
-+ //psxBranchTest();
- break;
-
- case 13: // Cause
-@@ -1027,6 +1033,23 @@ void intExecuteBlock() {
- while (!branch2) execI();
+-OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
++OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); psxBranchTest(); }
+
+ // no exception
+ static inline void psxNULLne(psxRegisters *regs) {
+@@ -1167,18 +1169,20 @@ static void intReset() {
+ static inline void execI_(u8 **memRLUT, psxRegisters *regs) {
+ u32 pc = regs->pc;
+
+- addCycle(regs);
++ //addCycle(regs);
+ dloadStep(regs);
+
+ regs->pc += 4;
+ regs->code = fetch(regs, memRLUT, pc);
+ psxBSC[regs->code >> 26](regs, regs->code);
++ psxRegs.cycle += 2;
++ fetchNoCache(regs, memRLUT, regs->pc); // bus err check
+ }
+
+ static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
+ u32 pc = regs->pc;
+
+- addCycle(regs);
++ //addCycle(regs);
+ dloadStep(regs);
+
+ if (execBreakCheck(regs, pc))
+@@ -1187,6 +1191,8 @@ static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
+ regs->pc += 4;
+ regs->code = fetch(regs, memRLUT, pc);
+ psxBSC[regs->code >> 26](regs, regs->code);
++ psxRegs.cycle += 2;
++ fetchNoCache(regs, memRLUT, regs->pc); // bus err check
+ }
+
+ static void intExecute() {
+@@ -1216,6 +1222,30 @@ void intExecuteBlock(enum blockExecCaller caller) {
+ execI_(memRLUT, regs_);