+#if 1
+ // have to map these further to keep tcache close to .text
+ mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE,
+ MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+ if (mem_readtab == MAP_FAILED) {
+ fprintf(stderr, "failed to map mem tables\n");
+ exit(1);
+ }
+ mem_writetab = mem_readtab + 0x100000;
+
+ // 1st level lookup:
+ // 0: direct mem
+ // 1: use 2nd lookup
+ // 2nd level lookup:
+ // 0: direct mem variable
+ // 1: memhandler
+
+ // default/unmapped memhandlers
+ for (i = 0; i < 0x100000; i++) {
+ //map_item(&mem_readtab[i], mem_unmrtab, 1);
+ map_l1_mem(mem_readtab, i, 0, 0x1000, unmapped_mem);
+ map_item(&mem_writetab[i], mem_unmwtab, 1);
+ }
+
+ // RAM and it's mirrors
+ for (i = 0; i < (0x800000 >> 12); i++) {
+ map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
+ map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
+ map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
+ }
+ map_ram_write();
+
+ // BIOS and it's mirrors
+ for (i = 0; i < (0x80000 >> 12); i++) {
+ map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
+ map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
+ }
+
+ // scratchpad
+ map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
+ map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
+
+ // I/O
+ map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
+ map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
+
+ // L2
+ // unmapped tables
+ for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
+ map_item(&mem_unmwtab[i], write_mem_dummy, 1);
+
+ // fill IO tables
+ for (i = 0; i < 0x1000/4; i++) {
+ map_item(&mem_iortab[i], &psxH[0x1000], 0);
+ map_item(&mem_iowtab[i], &psxH[0x1000], 0);
+ }
+ for (; i < 0x1000/4 + 0x1000/2; i++) {
+ map_item(&mem_iortab[i], &psxH[0x1000], 0);
+ map_item(&mem_iowtab[i], &psxH[0x1000], 0);
+ }
+ for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
+ map_item(&mem_iortab[i], &psxH[0x1000], 0);
+ map_item(&mem_iowtab[i], &psxH[0x1000], 0);
+ }
+
+ map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
+ map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
+ map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
+ map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
+ map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
+ map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
+ map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
+ map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
+ map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
+ map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
+// map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
+// map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
+ map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
+ map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
+
+ map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
+ map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
+ map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
+ map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
+ map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
+ map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
+ map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
+ map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
+ map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
+ map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
+ map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
+ map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
+ map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
+ map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
+
+ map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
+ map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
+ map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
+ map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
+ map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
+
+ // write(u32 data)
+ map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
+ map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
+ map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
+ map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
+ map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
+ map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
+// map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
+// map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
+ map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
+
+ map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
+ map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
+ map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
+ map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
+
+ map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
+ map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
+ map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
+ map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
+ map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
+
+ for (i = 0x1c00; i < 0x1e00; i += 2) {
+ map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
+ map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
+ }
+
+ // misc
+ map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
+ for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
+ map_item(&mem_ffwtab[i], write_biu, 1);