+ movea.l #0xa10003, a0
+ bsr sync_with_teensy /* trashes d3 */
+ move.l d0, (-4,a7)
+
+sync_hvc:
+ addq.l #1, d6 /* attempt counter */
+
+ /* set up for progress vram write (x,y - tile #) */
+ /* GFX_WRITE_VRAM_ADDR(0xc000 + (x + 64 * y) * 2) */
+ /* d = d5 + '0' - 32 + 0xB000/32 - 128 = d5 + 0x510 */
+ move.l #(0x40000003 | ((36 + 64*1) << 17)), (a3)
+ add.w #0x510, d5
+ move.w d5, (a5)
+ move.w #('/'+0x4e0), (a5)
+ move.w #('4'+0x4e0), (a5)
+
+ lea hexchars, a1
+ move.l #(0x40000003 | ((31 + 64*2) << 17)), (a3)
+ moveq.l #8-1, d5
+0:
+ rol.l #4, d3
+ move.b d3, d4
+ and.l #0x0f, d4
+ move.b (d4,a1), d4
+ add.w #0x4e0, d4
+ move.w d4, (a5)
+ dbra d5, 0b
+
+ movea.l #0xc00008, a0
+ movea.l #0x3ff000, a1
+ movea.l #0xffffe0, a2
+
+ /* wait for active display */
+ moveq.l #3, d2
+0:
+ btst d2, (a4) /* 8 */
+ beq.s 0b /* 10 */
+0:
+ btst d2, (a4)
+ bne.s 0b
+
+ /* flood the VDP FIFO */
+.rept 5
+ move.w d0, (a5)
+.endr
+
+ /* these seem stable for both 50Hz/60Hz */
+ move.l (a0), (a1)+ /* #0xff07ff09 */
+ move.l (a0), (a1)+ /* #0xff00ff11 */
+ move.l (a0), (a1)+ /* #0xff18ff1a */
+ move.l (a0), (a1)+ /* #0xff21ff23 */
+ move.l (a0), (a1)+ /* #0xff2aff28 */
+ move.l (a0), (a1)+ /* #0xff33ff34 */
+ move.l (a0), (a1)+ /* #0xff3cff3e */
+ move.l (a0), (a1)+ /* #0xff45ff47 */
+
+ /* as long as exactly 8 or more RAM writes are performed here, */
+ /* after multiple tries RAM refresh somehow eventually syncs */
+ /* after cold boot, only 50Hz syncs to always same values though, */
+ /* so values below are 50Hz */
+ move.l (a0), (a2)+ /* #0xff4eff4f */
+ move.l (a0), (a2)+ /* #0xff58ff59 */
+ move.l (a0), (a2)+ /* #0xff60ff62 */
+ move.l (a0), (a2)+ /* #0xff69ff6b */
+ move.l (a0), (a2)+ /* #0xff72ff74 */
+ move.l (a0), (a2)+ /* #0xff7bff7c */
+ move.l (a0), (a2)+ /* #0xff83ff85 */
+ move.l (a0), (a2)+ /* #0xff8eff8f */