+ if (!(Pico32x.regs[0] & P32XS_nRES)) {
+ msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
+ return; // rare
+ }
+
+ now = msh2.m68krcycles_done;
+ if (CYCLES_GT(now, ssh2.m68krcycles_done))
+ now = ssh2.m68krcycles_done;
+ timer_cycles = now;
+
+ while (CYCLES_GT(m68k_target, now))
+ {
+ if (event_time_next && CYCLES_GE(now, event_time_next))
+ p32x_run_events(now);
+
+ target = m68k_target;
+ if (event_time_next && CYCLES_GT(target, event_time_next))
+ target = event_time_next;
+
+ while (CYCLES_GT(target, now))
+ {
+ elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target,
+ target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
+ m68k_target - now, Pico32x.emu_flags);
+
+ if (!(ssh2.state & SH2_IDLE_STATES)) {
+ cycles = target - ssh2.m68krcycles_done;
+ if (cycles > 0) {
+ run_sh2(&ssh2, cycles);
+
+ if (event_time_next && CYCLES_GT(target, event_time_next))
+ target = event_time_next;
+ }
+ }
+
+ if (!(msh2.state & SH2_IDLE_STATES)) {
+ cycles = target - msh2.m68krcycles_done;
+ if (cycles > 0) {
+ run_sh2(&msh2, cycles);
+
+ if (event_time_next && CYCLES_GT(target, event_time_next))
+ target = event_time_next;
+ }
+ }
+
+ now = target;
+ if (!(msh2.state & SH2_IDLE_STATES)) {
+ if (CYCLES_GT(now, msh2.m68krcycles_done))
+ now = msh2.m68krcycles_done;
+ }
+ if (!(ssh2.state & SH2_IDLE_STATES)) {
+ if (CYCLES_GT(now, ssh2.m68krcycles_done))
+ now = ssh2.m68krcycles_done;
+ }
+ }
+
+ p32x_timers_do(now - timer_cycles);
+ timer_cycles = now;
+ }
+
+ // advance idle CPUs
+ if (msh2.state & SH2_IDLE_STATES) {
+ if (CYCLES_GT(m68k_target, msh2.m68krcycles_done))
+ msh2.m68krcycles_done = m68k_target;
+ }
+ if (ssh2.state & SH2_IDLE_STATES) {
+ if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done))
+ ssh2.m68krcycles_done = m68k_target;
+ }
+}
+
+#define STEP_68K 24
+
+void sync_sh2s_lockstep(unsigned int m68k_target)
+{
+ unsigned int mcycles;
+
+ mcycles = msh2.m68krcycles_done;
+ if (ssh2.m68krcycles_done < mcycles)
+ mcycles = ssh2.m68krcycles_done;
+
+ while (mcycles < m68k_target) {
+ mcycles += STEP_68K;
+ sync_sh2s_normal(mcycles);
+ }
+}
+
+#define CPUS_RUN(m68k_cycles) do { \
+ if (PicoAHW & PAHW_MCD) \
+ pcd_run_cpus(m68k_cycles); \
+ else \
+ SekRunM68k(m68k_cycles); \
+ \
+ if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \
+ && !Pico.m.z80_reset && (PicoOpt & POPT_EN_Z80)) \
+ PicoSyncZ80(SekCyclesDone()); \
+ if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
+ p32x_sync_sh2s(SekCyclesDone()); \
+} while (0)
+
+#define PICO_32X
+#define PICO_CD