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some new cpu debug code
[picodrive.git]
/
pico
/
32x
/
32x.c
diff --git
a/pico/32x/32x.c
b/pico/32x/32x.c
index
a6f0a51
..
d0110c1
100644
(file)
--- a/
pico/32x/32x.c
+++ b/
pico/32x/32x.c
@@
-29,11
+29,10
@@
static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
}
}
}
}
-//
if !nested_call, must sync CPUs before calling thi
s
-void p32x_update_irls(SH2 *active_sh2)
+//
MUST specify active_sh2 when called from sh2 memhandler
s
+void p32x_update_irls(SH2 *active_sh2
, int m68k_cycles
)
{
int irqs, mlvl = 0, slvl = 0;
{
int irqs, mlvl = 0, slvl = 0;
- int m68k_cycles = 0;
int mrun, srun;
if (active_sh2 != NULL)
int mrun, srun;
if (active_sh2 != NULL)
@@
-51,13
+50,19
@@
void p32x_update_irls(SH2 *active_sh2)
slvl++;
slvl *= 2;
slvl++;
slvl *= 2;
- mrun = sh2_irl_irq(&msh2, mlvl, active_sh2
!= NULL
);
- if (mrun)
+ mrun = sh2_irl_irq(&msh2, mlvl, active_sh2
== &msh2
);
+ if (mrun)
{
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
+ if (active_sh2 == &msh2)
+ sh2_end_run(active_sh2, 1);
+ }
- srun = sh2_irl_irq(&ssh2, slvl, active_sh2
!= NULL
);
- if (srun)
+ srun = sh2_irl_irq(&ssh2, slvl, active_sh2
== &ssh2
);
+ if (srun)
{
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
+ if (active_sh2 == &ssh2)
+ sh2_end_run(active_sh2, 1);
+ }
elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
}
elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
}
@@
-68,9
+73,9
@@
void Pico32xStartup(void)
// TODO: OOM handling
PicoAHW |= PAHW_32X;
// TODO: OOM handling
PicoAHW |= PAHW_32X;
- sh2_init(&msh2, 0);
+ sh2_init(&msh2, 0
, &ssh2
);
msh2.irq_callback = sh2_irq_cb;
msh2.irq_callback = sh2_irq_cb;
- sh2_init(&ssh2, 1);
+ sh2_init(&ssh2, 1
, &msh2
);
ssh2.irq_callback = sh2_irq_cb;
PicoMemSetup32x();
ssh2.irq_callback = sh2_irq_cb;
PicoMemSetup32x();
@@
-80,8
+85,8
@@
void Pico32xStartup(void)
if (!Pico.m.pal)
Pico32x.vdp_regs[0] |= P32XV_nPAL;
if (!Pico.m.pal)
Pico32x.vdp_regs[0] |= P32XV_nPAL;
- PREG8(
Pico32xMem->sh2_peri_regs[0]
, 4) =
- PREG8(
Pico32xMem->sh2_peri_regs[1]
, 4) = 0x84; // SCI SSR
+ PREG8(
msh2.peri_regs
, 4) =
+ PREG8(
ssh2.peri_regs
, 4) = 0x84; // SCI SSR
rendstatus_old = -1;
rendstatus_old = -1;
@@
-170,7
+175,7
@@
void PicoReset32x(void)
{
if (PicoAHW & PAHW_32X) {
Pico32x.sh2irqs |= P32XI_VRES;
{
if (PicoAHW & PAHW_32X) {
Pico32x.sh2irqs |= P32XI_VRES;
- p32x_update_irls(NULL);
+ p32x_update_irls(NULL
, SekCyclesDoneT2()
);
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
p32x_pwm_ctl_changed();
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
p32x_pwm_ctl_changed();
@@
-218,7
+223,7
@@
static void p32x_start_blank(void)
}
Pico32x.sh2irqs |= P32XI_VINT;
}
Pico32x.sh2irqs |= P32XI_VINT;
- p32x_update_irls(NULL);
+ p32x_update_irls(NULL
, SekCyclesDoneT2()
);
p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
}
p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
}
@@
-270,8
+275,7
@@
void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
p32x_event_schedule(now, event, after);
left_to_next = (event_time_next - now) * 3;
p32x_event_schedule(now, event, after);
left_to_next = (event_time_next - now) * 3;
- if (sh2_cycles_left(sh2) > left_to_next)
- sh2_end_run(sh2, left_to_next);
+ sh2_end_run(sh2, left_to_next);
}
static void run_events(unsigned int until)
}
static void run_events(unsigned int until)
@@
-335,7
+339,7
@@
static inline void run_sh2(SH2 *sh2, int m68k_cycles)
// note: recursive call
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
{
// note: recursive call
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
{
- SH2 *osh2 =
&sh2s[sh2->is_slave ^ 1]
;
+ SH2 *osh2 =
sh2->other_sh2
;
int left_to_event;
int m68k_cycles;
int left_to_event;
int m68k_cycles;
@@
-517,7
+521,7
@@
void Pico32xStateLoaded(int is_early)
SekCycleCnt = 0;
sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
SekCycleCnt = 0;
sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
- p32x_update_irls(NULL);
+ p32x_update_irls(NULL
, SekCycleCntT
);
p32x_pwm_state_loaded();
run_events(SekCycleCntT);
}
p32x_pwm_state_loaded();
run_events(SekCycleCntT);
}