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32x: fix some more timing problems
[picodrive.git]
/
pico
/
32x
/
memory.c
diff --git
a/pico/32x/memory.c
b/pico/32x/memory.c
index
5ede2ea
..
45c192d
100644
(file)
--- a/
pico/32x/memory.c
+++ b/
pico/32x/memory.c
@@
-213,7
+213,7
@@
static u32 p32x_reg_read16(u32 a)
}
if ((a & 0x30) == 0x30)
}
if ((a & 0x30) == 0x30)
- return p32x_pwm_read16(a, SekCyclesDoneT());
+ return p32x_pwm_read16(a,
NULL,
SekCyclesDoneT());
out:
return Pico32x.regs[a / 2];
out:
return Pico32x.regs[a / 2];
@@
-237,15
+237,21
@@
static void p32x_reg_write8(u32 a, u32 d)
r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
return;
case 3: // irq ctl
r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
return;
case 3: // irq ctl
- if ((d & 1)
&&
!(Pico32x.sh2irqi[0] & P32XI_CMD)) {
+ if ((d & 1)
!= !
!(Pico32x.sh2irqi[0] & P32XI_CMD)) {
p32x_sync_sh2s(SekCyclesDoneT());
p32x_sync_sh2s(SekCyclesDoneT());
- Pico32x.sh2irqi[0] |= P32XI_CMD;
- p32x_update_irls(NULL);
+ if (d & 1)
+ Pico32x.sh2irqi[0] |= P32XI_CMD;
+ else
+ Pico32x.sh2irqi[0] &= ~P32XI_CMD;
+ p32x_update_irls(NULL, SekCyclesDoneT2());
}
}
- if (
(d & 2) &&
!(Pico32x.sh2irqi[1] & P32XI_CMD)) {
+ if (
!!(d & 2) != !
!(Pico32x.sh2irqi[1] & P32XI_CMD)) {
p32x_sync_sh2s(SekCyclesDoneT());
p32x_sync_sh2s(SekCyclesDoneT());
- Pico32x.sh2irqi[1] |= P32XI_CMD;
- p32x_update_irls(NULL);
+ if (d & 2)
+ Pico32x.sh2irqi[1] |= P32XI_CMD;
+ else
+ Pico32x.sh2irqi[1] &= ~P32XI_CMD;
+ p32x_update_irls(NULL, SekCyclesDoneT2());
}
return;
case 5: // bank
}
return;
case 5: // bank
@@
-346,7
+352,7
@@
static void p32x_reg_write16(u32 a, u32 d)
}
// PWM
else if ((a & 0x30) == 0x30) {
}
// PWM
else if ((a & 0x30) == 0x30) {
- p32x_pwm_write16(a, d, SekCyclesDoneT());
+ p32x_pwm_write16(a, d,
NULL,
SekCyclesDoneT());
return;
}
return;
}
@@
-456,7
+462,7
@@
static u32 p32x_sh2reg_read16(u32 a, int cpuid)
return r[a / 2];
}
if ((a & 0x30) == 0x30) {
return r[a / 2];
}
if ((a & 0x30) == 0x30) {
- return p32x_pwm_read16(a, sh2_cycles_done_m68k(&sh2s[cpuid]));
+ return p32x_pwm_read16(a,
&sh2s[cpuid],
sh2_cycles_done_m68k(&sh2s[cpuid]));
}
return 0;
}
return 0;
@@
-481,7
+487,7
@@
static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
Pico32x.sh2_regs[0] |= d & 0x80;
if (d & 1)
p32x_pwm_schedule_sh2(&sh2s[cpuid]);
Pico32x.sh2_regs[0] |= d & 0x80;
if (d & 1)
p32x_pwm_schedule_sh2(&sh2s[cpuid]);
- p32x_update_irls(&sh2s[cpuid]);
+ p32x_update_irls(&sh2s[cpuid]
, 0
);
return;
case 5: // H count
d &= 0xff;
return;
case 5: // H count
d &= 0xff;
@@
-532,7
+538,7
@@
static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
}
// PWM
else if ((a & 0x30) == 0x30) {
}
// PWM
else if ((a & 0x30) == 0x30) {
- p32x_pwm_write16(a, d, sh2_cycles_done_m68k(&sh2s[cpuid]));
+ p32x_pwm_write16(a, d,
&sh2s[cpuid],
sh2_cycles_done_m68k(&sh2s[cpuid]));
return;
}
return;
}
@@
-555,7
+561,7
@@
static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
return;
irls:
return;
irls:
- p32x_update_irls(&sh2s[cpuid]);
+ p32x_update_irls(&sh2s[cpuid]
, 0
);
}
// ------------------------------------------------------------------
}
// ------------------------------------------------------------------