+
+ // WDT timers
+ for (i = 0; i < 2; i++) {
+ void *pregs = Pico32xMem->sh2_peri_regs[i];
+ if (PREG8(pregs, 0x80) & 0x20) { // TME
+ timer_cycles[i] += cycles;
+ cnt = PREG8(pregs, 0x81);
+ while (timer_cycles[i] >= timer_tick_cycles[i]) {
+ timer_cycles[i] -= timer_tick_cycles[i];
+ cnt++;
+ }
+ if (cnt >= 0x100) {
+ int level = PREG8(pregs, 0xe3) >> 4;
+ int vector = PREG8(pregs, 0xe4) & 0x7f;
+ elprintf(EL_32X, "%csh2 WDT irq (%d, %d)",
+ i ? 's' : 'm', level, vector);
+ sh2_internal_irq(&sh2s[i], level, vector);
+ cnt &= 0xff;
+ }
+ PREG8(pregs, 0x81) = cnt;
+ }
+ }
+}
+
+static int p32x_pwm_schedule_(void)
+{
+ int tm;
+
+ if (Pico32x.emu_flags & P32XF_PWM_PEND)
+ return 0; // already scheduled
+ if (Pico32x.sh2irqs & P32XI_PWM)
+ return 0; // previous not acked
+ if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 1))
+ return 0; // masked by everyone
+
+ Pico32x.emu_flags |= P32XF_PWM_PEND;
+ tm = (Pico32x.regs[0x30 / 2] & 0x0f00) >> 8;
+ tm = ((tm - 1) & 0x0f) + 1;
+ return pwm_cycles * tm / 3;
+}
+
+void p32x_pwm_schedule(unsigned int now)
+{
+ int after = p32x_pwm_schedule_();
+ if (after != 0)
+ p32x_event_schedule(now, P32X_EVENT_PWM, after);
+}
+
+void p32x_pwm_schedule_sh2(SH2 *sh2)
+{
+ int after = p32x_pwm_schedule_();
+ if (after != 0)
+ p32x_event_schedule_sh2(sh2, P32X_EVENT_PWM, after);