+ @ remember which exception vector we came from (increment counter for debug)\r
+ mov r0, #shared_ctl\r
+ add r0, r0, r12, lsl #2\r
+ ldr r1, [r0]\r
+ add r1, r1, #1\r
+ str r1, [r0]\r
+ \r
+ @ remember last lr (for debug)\r
+ mov r0, #shared_ctl\r
+ add r0, r0, #0x20\r
+ str lr, [r0]\r
+\r
+ @ ready to take first job-interrupt\r
+wait_for_irq:\r
+ mrs r0, cpsr\r
+ bic r0, r0, #0x80\r
+ msr cpsr_c, r0 @ enable interrupts\r
+\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c7, c0, 4 @ wait for IRQ\r
+@ mcr p15, 0, r0, c15, c8, 2\r
+ nop\r
+ nop\r
+ b .b_reserved\r
+\r