+static int t_32x_md_fb(void)
+{
+ u8 *fbb = (u8 *)0x840000;
+ u16 *fbw = (u16 *)fbb;
+ u32 *fbl = (u32 *)fbb;
+ u8 *fob = (u8 *)0x860000;
+ u16 *fow = (u16 *)fob;
+ u32 *fol = (u32 *)fob;
+ int ok = 1;
+
+ fbl[0] = 0x12345678;
+ fol[1] = 0x89abcdef;
+ mem_barrier();
+ expect(ok, fbw[1], 0x5678);
+ expect(ok, fow[2], 0x89ab);
+ fbb[0] = 0;
+ fob[1] = 0;
+ fbw[1] = 0;
+ fow[2] = 0;
+ fow[3] = 1;
+ mem_barrier();
+ fow[3] = 0x200;
+ mem_barrier();
+ expect(ok, fol[0], 0x12340000);
+ expect(ok, fbl[1], 0x89ab0201);
+ return ok;
+}
+
+static int t_32x_sh_fb(void)
+{
+ u32 *fbl = (u32 *)0x840000;
+ u8 *r8 = (u8 *)0xa15100;
+ int ok = 1;
+
+ if (read8(r8) & 0x80)
+ write8(r8, 0x00); // FM=0
+ fbl[0] = 0x12345678;
+ fbl[1] = 0x89abcdef;
+ mem_barrier();
+ write8(r8, 0x80); // FM=1
+ x32_cmd(CMD_WRITE8, 0x24000000, 0, 0); // should ignore
+ x32_cmd(CMD_WRITE8, 0x24020001, 0, 0); // ignore
+ x32_cmd(CMD_WRITE16, 0x24000002, 0, 0); // ok
+ x32_cmd(CMD_WRITE16, 0x24020000, 0, 0); // ignore
+ x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1);
+ write8(r8, 0x00); // FM=0
+ mem_barrier();
+ expect(ok, fbl[0], 0x12340000);
+ expect(ok, fbl[1], 0x5aabcda5);
+ return ok;
+}
+
+static int t_32x_irq(void)
+{
+ u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
+ u16 *m_icnt = (u16 *)fbl_icnt;
+ u16 *s_icnt = m_icnt + 8;
+ u32 *r = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r;
+ u8 *r8 = (u8 *)r;
+ int ok = 1, i;
+
+ write8(r, 0x00); // FM=0
+ r[0x2c/4] = 0;
+ mem_barrier();
+ for (i = 0; i < 8; i++)
+ write32(&fbl_icnt[i], 0);
+ mem_barrier();
+ write16(&r16[0x02/2], 0xfffd); // INTM+unused_bits
+ mem_barrier();
+ expect(ok, r16[0x02/2], 1);
+ x32_cmd(CMD_WRITE8, 0x20004001, 2, 0); // unmask cmd
+ x32_cmd(CMD_WRITE8, 0x20004001, 2, 1); // unmask cmd slave
+ burn10(10);
+ write8(r, 0x00); // FM=0 (hangs without)
+ mem_barrier();
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r8 [0x2c], 4);
+ expect(ok, r8 [0x2d], 0);
+ expect(ok, r16[0x2e/2], 0); // no exception_index
+ expect(ok, m_icnt[4], 1);
+ expect(ok, s_icnt[4], 0);
+ write16(&r16[0x02/2], 0xaaaa); // INTS+unused_bits
+ mem_barrier();
+ expect(ok, r16[0x02/2], 2);
+ burn10(10);
+ mem_barrier();
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r8 [0x2c], 4);
+ expect(ok, r8 [0x2d], 4);
+ expect(ok, r16[0x2e/2], 0); // no exception_index
+ write8(r, 0x00); // FM=0
+ mem_barrier();
+ expect(ok, m_icnt[4], 1);
+ expect(ok, s_icnt[4], 1);
+ for (i = 0; i < 8; i++) {
+ if (i == 4)
+ continue;
+ expect(ok, m_icnt[i], 0);
+ expect(ok, s_icnt[i], 0);
+ }
+ return ok;
+}
+
+static int t_32x_reg_w(void)
+{
+ u32 *r32 = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r32, old;
+ int ok = 1;
+
+ r32[0x08/4] = ~0;
+ r32[0x0c/4] = ~0;
+ r16[0x10/2] = ~0;
+ mem_barrier();
+ expect(ok, r32[0x08/4], 0xfffffe);
+ expect(ok, r32[0x0c/4], 0xffffff);
+ expect(ok, r16[0x10/2], 0xfffc);
+ mem_barrier();
+ r32[0x08/4] = r32[0x0c/4] = 0;
+ r16[0x10/2] = 0;
+ old = r16[0x06/2];
+ x32_cmd(CMD_WRITE16, 0x20004006, ~old, 0);
+ expect(ok, r16[0x06/2], old);
+ return ok;
+}
+
+// prepare for reset btn press tests
+static int t_32x_reset_prep(void)
+{
+ u32 *fbl = (u32 *)0x840000;
+ u32 *fbl_icnt = fbl + IRQ_CNT_FB_BASE / 4;
+ u32 *r32 = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r32;
+ u8 *r8 = (u8 *)r32;
+ int ok = 1, i;
+
+ expect(ok, r16[0x00/2], 0x83);
+ write8(r8, 0x00); // FM=0
+ r32[0x2c/4] = 0;
+ mem_barrier();
+ expect(ok, r8[0x8b] & ~2, 0);
+ for (i = 0; i < 8; i++)
+ write32(&fbl_icnt[i], 0x01000100);
+ x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 0); // unmask cmd
+ x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 1); // unmask slave
+ x32_cmd(CMD_SETSR, 0xf0, 0, 1); // mask slave irqs (on the cpu)
+ burn10(10);
+ write8(r8, 0x00); // FM=0
+ expect(ok, r32[0x2c/4], 0);
+ mem_barrier();
+ for (i = 0; i < 8; i++)
+ expect(ok, fbl_icnt[i], 0x01000100);
+
+ r16[0x04/2] = 0xffff;
+ r32[0x08/4] = 0x5a5a5a08;
+ r32[0x0c/4] = 0x5a5a5a0c;
+ r16[0x10/2] = 0x5a10;
+ r32[0x20/4] = 0x00005a20; // no x32_cmd
+ r32[0x24/4] = 0x5a5a5a24;
+ r32[0x28/4] = 0x5a5a5a28;
+ r32[0x2c/4] = 0x5a5a5a2c;
+ if (!(r16[0x00/2] & 0x8000)) {
+ wait_next_vsync();
+ r16[0x8a/2] = 0x0001;
+ mem_barrier();
+ for (i = 0; i < 220/2; i++)
+ write32(&fbl[i], 0);
+ r8 [0x81] = 1;
+ r16[0x82/2] = 0xffff;
+ r16[0x84/2] = 0xffff;
+ r16[0x86/2] = 0xffff;
+ r16[0x8a/2] = 0x0000;
+ r16[0x8c/2] = 0xffff;
+ r16[0x8e/2] = 0xffff;
+ r16[0x100/2] = 0;
+ }
+ return ok;
+}
+