+// 32X
+
+static int t_32x_init(void)
+{
+ void (*do_32x_enable)(void) = (void *)0xff0040;
+ u32 M_OK = MKLONG('M','_','O','K');
+ u32 S_OK = MKLONG('S','_','O','K');
+ u32 *r = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r;
+ int ok = 1;
+
+ expect(ok, r16[0x00/2], 0x82);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 0);
+ expect(ok, r16[0x06/2], 0);
+ expect(ok, r[0x14/4], 0);
+ expect(ok, r[0x18/4], 0);
+ expect(ok, r[0x1c/4], 0);
+ write32(&r[0x20/4], 0); // master resp
+ write32(&r[0x24/4], 0); // slave resp
+
+ // could just set RV, but BIOS reads ROM, so can't
+ memcpy_(do_32x_enable, x32x_enable,
+ x32x_enable_end - x32x_enable);
+ do_32x_enable();
+
+ expect(ok, r16[0x00/2], 0x83);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 0);
+ expect(ok, r16[0x06/2], 1); // RV
+ expect(ok, r[0x14/4], 0);
+ expect(ok, r[0x18/4], 0);
+ expect(ok, r[0x1c/4], 0);
+ expect(ok, r[0x20/4], M_OK);
+ while (!read16(&r16[0x24/2]))
+ ;
+ expect(ok, r[0x24/4], S_OK);
+ return ok;
+}
+
+static void x32_cmd(enum x32x_cmd cmd, u16 is_slave)
+{
+ u16 v, *r = (u16 *)0xa15120;
+ u16 cmd_s = cmd | (is_slave << 15);
+ write16(r, cmd_s);
+ mem_barrier();
+ while ((v = read16(r)) == cmd_s)
+ burn10(1);
+ if (v != 0)
+ printf("cmd clr: %x\n", v);
+}
+
+static int t_32x_echo(void)
+{
+ u16 *r = (u16 *)0xa15120;
+ int ok = 1;
+
+ write16(&r[0x02/2], 0x1234);
+ x32_cmd(CMD_ECHO, 0);
+ expect(ok, r[0x04/2], 0x1234);
+ write16(&r[0x02/2], 0x2345);
+ // mysteriously broken (random hangs)
+ //x32_cmd(CMD_ECHO, 1);
+ //expect(ok, r[0x04/2], 0x8345);
+ return ok;
+}
+
+static int t_32x_md_rom(void)
+{
+ u32 *rl = (u32 *)0;
+ int ok = 1;
+
+ expect(ok, rl[0x004/4], 0x880200);
+ expect(ok, rl[0x100/4], 0x53454741);
+ expect(ok, rl[0x70/4], 0);
+ write32(&rl[0x70/4], ~0);
+ write32(&rl[0x78/4], ~0);
+ mem_barrier();
+ expect(ok, rl[0x70/4], ~0);
+ expect(ok, rl[0x78/4], 0x8802ae);
+ // not tested: with RV 0x880000/0x900000 hangs
+ return ok;
+}
+
+enum {
+ T_MD = 0,
+ T_32 = 1, // 32X
+};
+