+static int t_irq_ack_h_v_2(void)
+{
+ u16 *ram = (u16 *)0xfff000;
+ u8 *ram8 = (u8 *)0xfff000;
+ u16 s0, s1;
+ int ok = 1;
+
+ ram[0] = ram[1] = ram[2] =
+ ram[4] = ram[5] = ram[6] = 0;
+ memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
+ memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
+ VDP_setReg(10, 0);
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ while (read8(VDP_HV_COUNTER) != 226)
+ ;
+ s0 = read16(VDP_CTRL_PORT);
+ test_h_v_2();
+ s1 = read16(VDP_CTRL_PORT);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+
+ expect(ok, ram[0], 2); // hint count
+ expect(ok, ram8[2], 226); // hint first line
+ expect(ok, ram8[4], 226); // hint last line
+ expect(ok, ram[4], 0); // vint count
+ expect(ok, ram8[10], 0); // vint line
+ expect_bits(ok, s0, SR_F, SR_F);
+ expect_bits(ok, s1, 0, SR_F);
+ return ok;
+}
+
+static void t_irq_f_flag(void)
+{
+ memcpy_((void *)0xff0140, test_f_vint, test_f_vint_end - test_f_vint);
+ memset_((void *)0xff0000, 0, 10);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
+ test_f();
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+}
+
+static int t_irq_f_flag_h40(void)
+{
+ u8 f, *r = (u8 *)0xff0000;
+ int ok = 1;
+
+ t_irq_f_flag();
+
+ expect_bits(ok, r[0], 0, SR_F);
+ expect_bits(ok, r[1], 0, SR_F);
+ expect_bits(ok, r[2], 0, SR_F);
+ // hits 1-3 times in range 3-9, usually ~5
+ f = r[3] | r[4] | r[5] | r[6] | r[7];
+
+ expect_bits(ok, r[10], 0, SR_F);
+ expect_bits(ok, r[11], 0, SR_F);
+ expect_bits(ok, f, SR_F, SR_F);
+ return ok;
+}
+
+static int t_irq_f_flag_h32(void)
+{
+ u8 f, *r = (u8 *)0xff0000;
+ int ok = 1;
+
+ VDP_setReg(VDP_MODE4, 0x00);
+ t_irq_f_flag();
+ VDP_setReg(VDP_MODE4, 0x81);
+
+ expect_bits(ok, r[0], 0, SR_F);
+ expect_bits(ok, r[1], 0, SR_F);
+ // hits 1-3 times in range 2-7, usually 3
+ f = r[2] | r[3] | r[4] | r[5] | r[6] | r[7];
+
+ expect_bits(ok, r[8], 0, SR_F);
+ expect_bits(ok, r[9], 0, SR_F);
+ expect_bits(ok, r[10], 0, SR_F);
+ expect_bits(ok, r[11], 0, SR_F);
+ expect_bits(ok, f, SR_F, SR_F);
+ return ok;
+}
+
+// 32X
+
+#define IRQ_CNT_FB_BASE 0x1ff00
+
+// see do_cmd()
+static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
+{
+ u16 v, *r = (u16 *)0xa15120;
+ u8 *r8 = (u8 *)r;
+ u16 cmd_s = cmd | (is_slave << 15);
+ int i;
+
+ write32(&r[4/2], a0);
+ write32(&r[8/2], a1);
+ mem_barrier();
+ write16(r, cmd_s);
+ mem_barrier();
+ for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
+ burn10(1);
+ if (v != 0) {
+ printf("cmd clr: %x\n", v);
+ mem_barrier();
+ printf("exc m s: %02x %02x\n", r8[0x0e], r8[0x0f]);
+ write16(r, 0);
+ }
+ v = read16(&r[1]);
+ if (v != 0) {
+ printf("cmd err: %x\n", v);
+ write16(&r[1], 0);
+ }
+}
+
+static int t_32x_reset_btn(void)
+{
+ void (*do_32x_disable)(void) = (void *)0xff0040;
+ u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
+ u16 *m_icnt = (u16 *)fbl_icnt;
+ u16 *s_icnt = m_icnt + 8;
+ u32 *r32 = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r32, i, s;
+ u8 *r8 = (u8 *)r32;
+ u32 *rl = (u32 *)0;
+ int ok = 1;
+
+ if (!(read16(r16) & 1))
+ return R_SKIP;
+
+ expect(ok, r16[0x00/2], 0x8083);
+
+ write8(r8, 0x00); // FM=0
+ mem_barrier();
+ expect(ok, r16[0x00/2], 0x83);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 3);
+ expect(ok, r16[0x06/2], 1); // RV (set in sega_gcc.s reset handler)
+ expect(ok, r32[0x08/4], 0x5a5a08);
+ expect(ok, r32[0x0c/4], 0x5a5a0c);
+ expect(ok, r16[0x10/2], 0x5a10);
+ expect(ok, r32[0x14/4], 0);
+ expect(ok, r32[0x18/4], 0);
+ expect(ok, r32[0x1c/4], 0);
+ expect(ok, r32[0x20/4], 0x00005a20);
+ expect(ok, r32[0x24/4], 0x5a5a5a24);
+ expect(ok, r32[0x28/4], 0x5a5a5a28);
+ expect(ok, r32[0x2c/4], 0x075a5a2c); // 7 - last_irq_vec
+ if (!(r16[0x00/2] & 0x8000)) {
+ expect(ok, r8 [0x81], 1);
+ expect(ok, r16[0x82/2], 1);
+ expect(ok, r16[0x84/2], 0xff);
+ expect(ok, r16[0x86/2], 0xffff);
+ expect(ok, r16[0x88/2], 0);
+ expect(ok, r8 [0x8b] & ~2, 0); // FEN toggles periodically?
+ expect(ok, r16[0x8c/2], 0);
+ expect(ok, r16[0x8e/2], 0);
+ // setup vdp for t_32x_init
+ r8 [0x81] = 0;
+ r16[0x82/2] = r16[0x84/2] = r16[0x86/2] = 0;
+ }
+ r32[0x20/4] = r32[0x24/4] = r32[0x28/4] = r32[0x2c/4] = 0;
+ for (s = 0; s < 2; s++)
+ {
+ x32_cmd(CMD_READ32, 0x20004000, 0, s); // not cleared by hw
+ expect_sh2(ok, s, r32[0x24/4], 0x02020000); // ADEN | cmd
+ // t_32x_sh_defaults will test the other bits
+ }
+ // setup for t_32x_sh_defaults
+ x32_cmd(CMD_WRITE8, 0x20004001, 0, 0);
+ x32_cmd(CMD_WRITE8, 0x20004001, 0, 1);
+
+ for (i = 0; i < 7; i++) {
+ expect(ok, m_icnt[i], 0x100);
+ expect(ok, s_icnt[i], 0x100);
+ }
+ expect(ok, m_icnt[7], 0x101); // VRES happened
+ expect(ok, s_icnt[7], 0x100); // masked on slave
+
+ x32_cmd(CMD_GETSR, 0, 0, 1);
+ expect_sh2(ok, 1, r32[0x24/4] & ~1, 0xf0); // still masked
+ x32_cmd(CMD_SETSR, 0x10, 0, 1);
+ expect(ok, r16[0x00/2], 0x8083);
+ write8(r8, 0x00); // FM=0
+ mem_barrier();
+ expect(ok, m_icnt[7], 0x101);
+ expect(ok, s_icnt[7], 0x101);
+ expect(ok, r32[0x2c/4], 0x00070000); // 7 - last_irq_vec
+ r32[0x2c/4] = 0;
+
+ memcpy_(do_32x_disable, x32x_disable,
+ x32x_disable_end - x32x_disable);
+ do_32x_disable();
+
+ expect(ok, r16[0x00/2], 0x82);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 3);
+ expect(ok, r16[0x06/2], 0); // RV cleared by x32x_disable
+ expect(ok, r32[0x08/4], 0x5a5a08);
+ expect(ok, r32[0x0c/4], 0x5a5a0c);
+ expect(ok, r16[0x10/2], 0x5a10);
+ expect(ok, rl[0x04/4], 0x000800);
+
+ // setup for t_32x_init, t_32x_sh_defaults
+ r16[0x04/2] = 0;
+ r16[0x10/2] = 0x1234; // warm reset indicator
+ mem_barrier();
+ expect(ok, r16[0x06/2], 0); // RV
+ return ok;
+}
+
+static int t_32x_init(void)
+{
+ void (*do_32x_enable)(void) = (void *)0xff0040;
+ u32 M_OK = MKLONG('M','_','O','K');
+ u32 S_OK = MKLONG('S','_','O','K');
+ u32 *r32 = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r32;
+ u8 *r8 = (u8 *)r32;
+ int i, ok = 1;
+
+ //v1070 = read32(0x1070);
+
+ /* what does REN mean exactly?
+ * Seems to be sometimes clear after reset */
+ for (i = 0; i < 1000000; i++)
+ if (read16(r16) & 0x80)
+ break;
+ expect(ok, r16[0x00/2], 0x82);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 0);
+ expect(ok, r16[0x06/2], 0);
+ expect(ok, r8 [0x08], 0);
+ //expect(ok, r32[0x08/4], 0); // garbage 24bit
+ expect(ok, r8 [0x0c], 0);
+ //expect(ok, r32[0x0c/4], 0); // garbage 24bit
+ if (r16[0x10/2] != 0x1234) // warm reset
+ expect(ok, r16[0x10/2], 0xffff);
+ expect(ok, r16[0x12/2], 0);
+ expect(ok, r32[0x14/4], 0);
+ expect(ok, r32[0x18/4], 0);
+ expect(ok, r32[0x1c/4], 0);
+ //expect(ok, r8 [0x81], 0); // VDP; hangs without ADEN
+ r32[0x20/4] = 0; // master resp
+ r32[0x24/4] = 0; // slave resp
+ r32[0x28/4] = 0;
+ r32[0x2c/4] = 0;
+
+ // check writable bits without ADEN
+ // 08,0c have garbage or old values (survive MD's power cycle)
+ write16(&r16[0x00/2], 0);
+ mem_barrier();
+ expect(ok, r16[0x00/2], 0x80);
+ write16(&r16[0x00/2], 0xfffe);
+ mem_barrier();
+ expect(ok, r16[0x00/2], 0x8082);
+ r16[0x00/2] = 0x82;
+ r16[0x02/2] = 0xffff;
+ r32[0x04/4] = 0xffffffff;
+ r32[0x08/4] = 0xffffffff;
+ r32[0x0c/4] = 0xffffffff;
+ r16[0x10/2] = 0xffff;
+ r32[0x14/4] = 0xffffffff;
+ r32[0x18/4] = 0xffffffff;
+ r32[0x1c/4] = 0xffffffff;
+ mem_barrier();
+ expect(ok, r16[0x00/2], 0x82);
+ expect(ok, r16[0x02/2], 0x03);
+ expect(ok, r16[0x04/2], 0x03);
+ expect(ok, r16[0x06/2], 0x07);
+ expect(ok, r32[0x08/4], 0x00fffffe);
+ expect(ok, r32[0x0c/4], 0x00ffffff);
+ expect(ok, r16[0x10/2], 0xfffc);
+ expect(ok, r32[0x14/4], 0);
+ expect(ok, r16[0x18/2], 0);
+ expect(ok, r16[0x1a/2], 0x0101);
+ expect(ok, r32[0x1c/4], 0);
+ r16[0x02/2] = 0;
+ r32[0x04/4] = 0;
+ r32[0x08/4] = 0;
+ r32[0x0c/4] = 0;
+ r16[0x1a/2] = 0;
+
+ // could just set RV, but BIOS reads ROM, so can't
+ memcpy_(do_32x_enable, x32x_enable,
+ x32x_enable_end - x32x_enable);
+ do_32x_enable();
+
+ expect(ok, r16[0x00/2], 0x83);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 0);
+ expect(ok, r16[0x06/2], 1); // RV
+ expect(ok, r32[0x14/4], 0);
+ expect(ok, r32[0x18/4], 0);
+ expect(ok, r32[0x1c/4], 0);
+ expect(ok, r32[0x20/4], M_OK);
+ while (!read16(&r16[0x24/2]))
+ ;
+ expect(ok, r32[0x24/4], S_OK);
+ write32(&r32[0x20/4], 0);
+ if (!(r16[0x00/2] & 0x8000)) {
+ expect(ok, r8 [0x81], 0);
+ expect(ok, r16[0x82/2], 0);
+ expect(ok, r16[0x84/2], 0);
+ expect(ok, r16[0x86/2], 0);
+ //expect(ok, r16[0x88/2], 0); // triggers fill?
+ expect(ok, r8 [0x8b] & ~2, 0);
+ expect(ok, r16[0x8c/2], 0);
+ expect(ok, r16[0x8e/2], 0);
+ }
+ return ok;
+}
+
+static int t_32x_echo(void)
+{
+ u16 *r16 = (u16 *)0xa15100;
+ int ok = 1;
+
+ r16[0x2c/2] = r16[0x2e/2] = 0;
+ x32_cmd(CMD_ECHO, 0x12340000, 0, 0);
+ expect_sh2(ok, 0, r16[0x26/2], 0x1234);
+ x32_cmd(CMD_ECHO, 0x23450000, 0, 1);
+ expect_sh2(ok, 1, r16[0x26/2], 0xa345);
+ expect(ok, r16[0x2c/2], 0); // no last_irq_vec
+ expect(ok, r16[0x2e/2], 0); // no exception_index
+ return ok;
+}
+
+static int t_32x_sh_defaults(void)
+{
+ u32 *r32 = (u32 *)0xa15120;
+ int ok = 1, s;
+
+ for (s = 0; s < 2; s++)
+ {
+ x32_cmd(CMD_READ32, 0x20004000, 0, s);
+ expect_sh2(ok, s, r32[0x04/4], 0x02000000); // ADEN
+ x32_cmd(CMD_READ32, 0x20004004, 0, s);
+ expect_sh2(ok, s, r32[0x04/4], 0x00004001); // Empty Rv
+ x32_cmd(CMD_READ32, 0x20004008, 0, s);
+ expect_sh2(ok, s, r32[0x04/4], 0);
+ x32_cmd(CMD_READ32, 0x2000400c, 0, s);
+ expect_sh2(ok, s, r32[0x04/4], 0);
+ x32_cmd(CMD_GETGBR, 0, 0, s);
+ expect_sh2(ok, s, r32[0x04/4], 0x20004000);
+ }
+ return ok;
+}
+
+static int t_32x_md_bios(void)
+{
+ void (*do_call_c0)(int a, int d) = (void *)0xff0040;
+ u8 *rmb = (u8 *)0xff0000;
+ u32 *rl = (u32 *)0;
+ int ok = 1;
+
+ memcpy_(do_call_c0, test_32x_b_c0,
+ test_32x_b_c0_end - test_32x_b_c0);
+ write8(rmb, 0);
+ do_call_c0(0xff0000, 0x5a);
+
+ expect(ok, rmb[0], 0x5a);
+ expect(ok, rl[0x04/4], 0x880200);
+ expect(ok, rl[0x10/4], 0x880212);
+ expect(ok, rl[0x94/4], 0x8802d8);
+ return ok;
+}
+
+static int t_32x_md_rom(void)
+{
+ u32 *rl = (u32 *)0;
+ int ok = 1;
+
+ expect(ok, rl[0x004/4], 0x880200);
+ expect(ok, rl[0x100/4], 0x53454741);
+ expect(ok, rl[0x70/4], 0);
+ write32(&rl[0x70/4], 0xa5123456);
+ write32(&rl[0x78/4], ~0);
+ mem_barrier();
+ expect(ok, rl[0x78/4], 0x8802ae);
+ expect(ok, rl[0x70/4], 0xa5123456);
+ //expect(ok, rl[0x1070/4], v1070);
+ write32(&rl[0x70/4], 0);
+ // with RV 0x880000/0x900000 hangs, can't test
+ return ok;
+}
+
+static int t_32x_md_fb(void)
+{
+ u8 *fbb = (u8 *)0x840000;
+ u16 *fbw = (u16 *)fbb;
+ u32 *fbl = (u32 *)fbb;
+ u8 *fob = (u8 *)0x860000;
+ u16 *fow = (u16 *)fob;
+ u32 *fol = (u32 *)fob;
+ int ok = 1;
+
+ fbl[0] = 0x12345678;
+ fol[1] = 0x89abcdef;
+ mem_barrier();
+ expect(ok, fbw[1], 0x5678);
+ expect(ok, fow[2], 0x89ab);
+ fbb[0] = 0;
+ fob[1] = 0;
+ fbw[1] = 0;
+ fow[2] = 0;
+ fow[3] = 1;
+ mem_barrier();
+ fow[3] = 0x200;
+ mem_barrier();
+ expect(ok, fol[0], 0x12340000);
+ expect(ok, fbl[1], 0x89ab0201);
+ return ok;
+}
+
+static int t_32x_sh_fb(void)
+{
+ u32 *fbl = (u32 *)0x840000;
+ u8 *r8 = (u8 *)0xa15100;
+ int ok = 1;
+
+ if (read8(r8) & 0x80)
+ write8(r8, 0x00); // FM=0
+ fbl[0] = 0x12345678;
+ fbl[1] = 0x89abcdef;
+ mem_barrier();
+ write8(r8, 0x80); // FM=1
+ x32_cmd(CMD_WRITE8, 0x24000000, 0, 0); // should ignore
+ x32_cmd(CMD_WRITE8, 0x24020001, 0, 0); // ignore
+ x32_cmd(CMD_WRITE16, 0x24000002, 0, 0); // ok
+ x32_cmd(CMD_WRITE16, 0x24020000, 0, 0); // ignore
+ x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1);
+ write8(r8, 0x00); // FM=0
+ mem_barrier();
+ expect(ok, fbl[0], 0x12340000);
+ expect(ok, fbl[1], 0x5aabcda5);
+ return ok;
+}
+
+static int t_32x_irq(void)
+{
+ u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
+ u16 *m_icnt = (u16 *)fbl_icnt;
+ u16 *s_icnt = m_icnt + 8;
+ u32 *r = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r;
+ u8 *r8 = (u8 *)r;
+ int ok = 1, i;
+
+ write8(r, 0x00); // FM=0
+ r[0x2c/4] = 0;
+ mem_barrier();
+ for (i = 0; i < 8; i++)
+ write32(&fbl_icnt[i], 0);
+ mem_barrier();
+ write16(&r16[0x02/2], 0xfffd); // INTM+unused_bits
+ mem_barrier();
+ expect(ok, r16[0x02/2], 1);
+ x32_cmd(CMD_WRITE8, 0x20004001, 2, 0); // unmask cmd
+ x32_cmd(CMD_WRITE8, 0x20004001, 2, 1); // unmask cmd slave
+ burn10(10);
+ write8(r, 0x00); // FM=0 (hangs without)
+ mem_barrier();
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r8 [0x2c], 4);
+ expect(ok, r8 [0x2d], 0);
+ expect(ok, r16[0x2e/2], 0); // no exception_index
+ expect(ok, m_icnt[4], 1);
+ expect(ok, s_icnt[4], 0);
+ write16(&r16[0x02/2], 0xaaaa); // INTS+unused_bits
+ mem_barrier();
+ expect(ok, r16[0x02/2], 2);
+ burn10(10);
+ mem_barrier();
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r8 [0x2c], 4);
+ expect(ok, r8 [0x2d], 4);
+ expect(ok, r16[0x2e/2], 0); // no exception_index
+ write8(r, 0x00); // FM=0
+ mem_barrier();
+ expect(ok, m_icnt[4], 1);
+ expect(ok, s_icnt[4], 1);
+ for (i = 0; i < 8; i++) {
+ if (i == 4)
+ continue;
+ expect(ok, m_icnt[i], 0);
+ expect(ok, s_icnt[i], 0);
+ }
+ return ok;
+}
+
+static int t_32x_reg_w(void)
+{
+ u32 *r32 = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r32, old;
+ int ok = 1;
+
+ r32[0x08/4] = ~0;
+ r32[0x0c/4] = ~0;
+ r16[0x10/2] = ~0;
+ mem_barrier();
+ expect(ok, r32[0x08/4], 0xfffffe);
+ expect(ok, r32[0x0c/4], 0xffffff);
+ expect(ok, r16[0x10/2], 0xfffc);
+ mem_barrier();
+ r32[0x08/4] = r32[0x0c/4] = 0;
+ r16[0x10/2] = 0;
+ old = r16[0x06/2];
+ x32_cmd(CMD_WRITE16, 0x20004006, ~old, 0);
+ expect(ok, r16[0x06/2], old);
+ return ok;
+}
+
+// prepare for reset btn press tests
+static int t_32x_reset_prep(void)
+{
+ u32 *fbl = (u32 *)0x840000;
+ u32 *fbl_icnt = fbl + IRQ_CNT_FB_BASE / 4;
+ u32 *r32 = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r32;
+ u8 *r8 = (u8 *)r32;
+ int ok = 1, i;
+
+ expect(ok, r16[0x00/2], 0x83);
+ write8(r8, 0x00); // FM=0
+ r32[0x2c/4] = 0;
+ mem_barrier();
+ expect(ok, r8[0x8b] & ~2, 0);
+ for (i = 0; i < 8; i++)
+ write32(&fbl_icnt[i], 0x01000100);
+ x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 0); // unmask cmd
+ x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 1); // unmask slave
+ x32_cmd(CMD_SETSR, 0xf0, 0, 1); // mask slave irqs (on the cpu)
+ burn10(10);
+ write8(r8, 0x00); // FM=0
+ expect(ok, r32[0x2c/4], 0);
+ mem_barrier();
+ for (i = 0; i < 8; i++)
+ expect(ok, fbl_icnt[i], 0x01000100);
+
+ r16[0x04/2] = 0xffff;
+ r32[0x08/4] = 0x5a5a5a08;
+ r32[0x0c/4] = 0x5a5a5a0c;
+ r16[0x10/2] = 0x5a10;
+ r32[0x20/4] = 0x00005a20; // no x32_cmd
+ r32[0x24/4] = 0x5a5a5a24;
+ r32[0x28/4] = 0x5a5a5a28;
+ r32[0x2c/4] = 0x5a5a5a2c;
+ if (!(r16[0x00/2] & 0x8000)) {
+ wait_next_vsync();
+ r16[0x8a/2] = 0x0001;
+ mem_barrier();
+ for (i = 0; i < 220/2; i++)
+ write32(&fbl[i], 0);
+ r8 [0x81] = 1;
+ r16[0x82/2] = 0xffff;
+ r16[0x84/2] = 0xffff;
+ r16[0x86/2] = 0xffff;
+ r16[0x8a/2] = 0x0000;
+ r16[0x8c/2] = 0xffff;
+ r16[0x8e/2] = 0xffff;
+ r16[0x100/2] = 0;
+ }
+ return ok;
+}
+
+enum {
+ T_MD = 0,
+ T_32 = 1, // 32X
+};
+