+static int t_tim_loop(void)
+{
+ u8 vcnt;
+ int ok = 1;
+
+ vdp_wait_for_line_0();
+ burn10(488*220/10);
+ vcnt = read8(VDP_HV_COUNTER);
+ mem_barrier();
+
+ //expect_range(ok, vcnt, 0x80, 0x80);
+ expect(ok, vcnt, 223);
+ return ok;
+}
+
+#define Z80_RD_V_CYCLES(b) (132 + (b) * 38 + 50 + 17)
+
+// 80 80 91 95-96
+static void z80_read_loop(u8 *zram, u16 src)
+{
+ const int pairs = 512 + 256;
+
+ zram[0x1000] = 2; // read loop, save vcnt
+ write16_z80le(&zram[0x1002], src); // src
+ write16_z80le(&zram[0x1004], 0x1100); // vcnt dst
+ write16_z80le(&zram[0x1006], pairs); // reads/2
+ zram[0x1100] = 0;
+ mem_barrier();
+
+ vdp_wait_for_line_0();
+ write16(0xa11100, 0x000);
+ burn10(Z80_RD_V_CYCLES(pairs) * 15 / 7 * 4 / 10);
+
+ write16(0xa11100, 0x100);
+ while (read16(0xa11100) & 0x100)
+ ;
+}
+
+static int t_tim_z80_ram(void)
+{
+ u8 *zram = (u8 *)0xa00000;
+ int ok = 1;
+
+ z80_read_loop(zram, 0);
+
+ expect(ok, zram[0x1000], 0);
+ expect_range(ok, zram[0x1100], 0x80, 0x80);
+ return ok;
+}
+
+static int t_tim_z80_ym(void)
+{
+ u8 *zram = (u8 *)0xa00000;
+ int ok = 1;
+
+ z80_read_loop(zram, 0x4000);
+
+ expect(ok, zram[0x1000], 0);
+ expect_range(ok, zram[0x1100], 0x80, 0x80);
+ return ok;
+}
+
+static int t_tim_z80_vdp(void)
+{
+ u8 *zram = (u8 *)0xa00000;
+ int ok = 1;
+
+ z80_read_loop(zram, 0x7f08);
+
+ expect(ok, zram[0x1000], 0);
+#ifndef PICO
+ expect_range(ok, zram[0x1100], 0x91, 0x91);
+#else
+ expect_range(ok, zram[0x1100], 0x8e, 0x91);
+#endif
+ return ok;
+}
+
+static int t_tim_z80_bank_rom(void)
+{
+ u8 *zram = (u8 *)0xa00000;
+ int i, ok = 1;
+
+ for (i = 0; i < 17; i++)
+ write8(0xa06000, 0); // bank 0
+
+ z80_read_loop(zram, 0x8000);
+
+ expect(ok, zram[0x1000], 0);
+#ifndef PICO
+ expect_range(ok, zram[0x1100], 0x95, 0x96);
+#else
+ expect_range(ok, zram[0x1100], 0x93, 0x96);
+#endif
+ return ok;
+}
+
+/* borderline too slow */
+#if 0
+static void do_vcnt_vb(void)
+{
+ const u32 *srhv = (u32 *)0xc00006; // to read SR and HV counter
+ u32 *ram = (u32 *)0xff0000;
+ u16 vcnt, vcnt_expect = 0;
+ u16 sr, count = 0;
+ u32 val, old;
+
+ vdp_wait_for_line_0();
+ old = read32(srhv);
+ *ram++ = old;
+ for (;;) {
+ val = read32(srhv);
+ vcnt = val & 0xff00;
+ if (vcnt == vcnt_expect)
+ continue;
+ sr = val >> 16;
+ if (vcnt == 0 && !(sr & SR_VB)) // not VB
+ break; // wrapped to start of frame
+// count++;
+ vcnt_expect += 0x100;
+ if (vcnt == vcnt_expect && !((sr ^ (old >> 16)) & SR_VB)) {
+ old = val;
+ continue;
+ }
+ // should have a vcnt jump here
+ *ram++ = old;
+ *ram++ = val;
+ vcnt_expect = vcnt;
+ old = val;
+ }
+ *ram++ = val;
+ *ram = count;
+ mem_barrier();
+}
+#endif
+
+static int t_tim_vcnt(void)
+{
+ const u32 *ram32 = (u32 *)0xff0000;
+ const u8 *ram = (u8 *)0xff0000;
+ u8 pal = read8(0xa10001) & 0x40;
+ u8 vc_jmp_b = pal ? 0x02 : 0xea;
+ u8 vc_jmp_a = pal ? 0xca : 0xe5;
+ u16 lines = pal ? 313 : 262;
+ int ok = 1;
+
+ do_vcnt_vb();
+ expect(ok, ram[0*4+2], 0); // line 0
+ expect_bits(ok, ram[0*4+1], 0, SR_VB);
+ expect(ok, ram[1*4+2], 223); // last no blank
+ expect_bits(ok, ram[1*4+1], 0, SR_VB);
+ expect(ok, ram[2*4+2], 224); // 1st blank
+ expect_bits(ok, ram[2*4+1], SR_VB, SR_VB);
+ expect(ok, ram[3*4+2], vc_jmp_b); // before jump
+ expect_bits(ok, ram[3*4+1], SR_VB, SR_VB);
+ expect(ok, ram[4*4+2], vc_jmp_a); // after jump
+ expect_bits(ok, ram[4*4+1], SR_VB, SR_VB);
+ expect(ok, ram[5*4+2], 0xfe); // before vb clear
+ expect_bits(ok, ram[5*4+1], SR_VB, SR_VB);
+ expect(ok, ram[6*4+2], 0xff); // after vb clear
+ expect_bits(ok, ram[6*4+1], 0, SR_VB);
+ expect(ok, ram[7*4+2], 0); // next line 0
+ expect_bits(ok, ram[7*4+1], 0, SR_VB);
+ expect(ok, ram32[8], lines - 1);
+ return ok;
+}
+
+static int t_tim_vdp_as_vram_w(void)
+{
+ int ok = 1;
+ u8 vcnt;
+
+ write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
+ vdp_wait_for_line_0();
+ write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
+ vcnt = read8(VDP_HV_COUNTER);
+ mem_barrier();
+
+ expect(ok, vcnt, 112*2-1);
+ return ok;
+}
+
+static int t_tim_vdp_as_cram_w(void)
+{
+ int ok = 1;
+ u8 vcnt;
+
+ write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
+ vdp_wait_for_line_0();
+ write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
+ vcnt = read8(VDP_HV_COUNTER);
+ mem_barrier();
+
+ setup_default_palette();
+
+#ifndef PICO
+ expect(ok, vcnt, 112);
+#else
+ expect_range(ok, vcnt, 111, 112);
+#endif
+ return ok;
+}
+
+static int t_irq_hint(void)
+{
+ u16 *ram = (u16 *)0xfff000;
+ u8 *ram8 = (u8 *)0xfff000;
+ u16 v_p, cnt_p;
+ int ok = 1;
+
+ // for more fun, disable the display
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
+
+ ram[0] = ram[1] = ram[2] = 0;
+ memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
+ VDP_setReg(10, 0);
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ while (read8(VDP_HV_COUNTER) != 229)
+ ;
+ // take the pending irq
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
+ move_sr(0x2000);
+ burn10(488 * 2 / 10);
+ move_sr(0x2700);
+ v_p = ram8[2];
+ cnt_p = ram[0];
+ ram[0] = ram[1] = ram[2] = 0;
+ // count irqs
+ move_sr(0x2000);
+ while (read8(VDP_HV_COUNTER) != 3)
+ ;
+ while (read8(VDP_HV_COUNTER) != 228)
+ ;
+ move_sr(0x2700);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+
+ expect(ok, v_p, 229); // pending irq trigger
+ expect(ok, cnt_p, 1);
+ expect(ok, ram[0], 225); // count
+ expect(ok, ram8[2], 0); // first line
+ expect(ok, ram8[4], 224); // last line
+ return ok;
+}
+
+static int t_irq_ack_v_h(void)
+{
+ u16 *ram = (u16 *)0xfff000;
+ u8 *ram8 = (u8 *)0xfff000;
+ u16 s0, s1, s2;
+ int ok = 1;
+
+ ram[0] = ram[1] = ram[2] =
+ ram[4] = ram[5] = ram[6] = 0;
+ memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
+ memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
+ VDP_setReg(10, 0);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0);
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ while (read8(VDP_HV_COUNTER) != 226)
+ ;
+ s0 = read16(VDP_CTRL_PORT);
+ s1 = move_sr_and_read(0x2500, VDP_CTRL_PORT);
+ burn10(666 / 10);
+ s2 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
+ burn10(488 / 10);
+ move_sr(0x2700);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+
+ expect(ok, ram[4], 1); // vint count
+ expect(ok, ram8[10], 226); // vint line
+ expect(ok, ram[0], 1); // hint count
+ expect(ok, ram8[2], 228); // hint line
+ expect_bits(ok, s0, SR_F, SR_F);
+ expect_bits(ok, s1, 0, SR_F);
+ expect_bits(ok, s2, 0, SR_F);
+ return ok;
+}
+
+static int t_irq_ack_h_v(void)
+{
+ u16 *ram = (u16 *)0xfff000;
+ u8 *ram8 = (u8 *)0xfff000;
+ u16 s0, s1, s[4];
+ int ok = 1;
+
+ ram[0] = ram[1] = ram[2] =
+ ram[4] = ram[5] = ram[6] = 0;
+ memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
+ memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
+ VDP_setReg(10, 0);
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ while (read8(VDP_HV_COUNTER) != 226)
+ ;
+ s0 = read16(VDP_CTRL_PORT);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
+ move_sr(0x2000);
+ burn10(666 / 10);
+ s1 = read16(VDP_CTRL_PORT);
+ write_and_read1(VDP_CTRL_PORT, 0x8000 | (VDP_MODE2 << 8)
+ | VDP_MODE2_MD | VDP_MODE2_IE0, s);
+ burn10(488 / 10);
+ move_sr(0x2700);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+
+ expect(ok, ram[0], 1); // hint count
+ expect(ok, ram8[2], 226); // hint line
+ expect(ok, ram[4], 1); // vint count
+ expect(ok, ram8[10], 228); // vint line
+ expect_bits(ok, s0, SR_F, SR_F);
+ expect_bits(ok, s1, SR_F, SR_F);
+ expect_bits(ok, s[0], SR_F, SR_F);
+ expect_bits(ok, s[1], SR_F, SR_F);
+ expect_bits(ok, s[2], 0, SR_F);
+ expect_bits(ok, s[3], 0, SR_F);
+ return ok;
+}
+