+static const u8 hcnt2tm[] =
+{
+ 0x0a, 0x1d, 0x31, 0x44, 0x58, 0x6b, 0x7f, 0x92,
+ 0xa6, 0xb9, 0xcc, 0x00, 0x00, 0x00, 0xe2, 0xf6
+};
+
+static int t_tim_ym_timer_z80(int is_b)
+{
+ u8 pal = read8(0xa10001) & 0x40;
+ u8 *zram = (u8 *)0xa00000;
+ u8 *z80 = zram;
+ u16 _68k_loops = 3420*(302+5+1)/7/10; // ~ (72*1024*2)/(3420./7)
+ u16 start, end, diff;
+ int ok = 1;
+
+ zram[0x1000] = 4 + is_b; // ym2612 timer a/b test
+ zram[0x1100] = zram[0x1101] = zram[0x1102] = zram[0x1103] = 0;
+ mem_barrier();
+
+ vdp_wait_for_line_0();
+ write16(0xa11100, 0x000);
+
+ burn10(_68k_loops + (Z80_C_DISPATCH + Z80_C_END_VCNT) * 15 / 7 / 10);
+
+ write16(0xa11100, 0x100);
+ while (read16(0xa11100) & 0x100)
+ ;
+ mem_barrier();
+ expect(ok, zram[0x1000], 0);
+ (void)hcnt2tm;
+ //start = ((u16)zram[0x1102] << 8) | hcnt2tm[zram[0x1103] >> 4];
+ //end = ((u16)zram[0x1100] << 8) | hcnt2tm[zram[0x1101] >> 4];
+ start = zram[0x1102];
+ end = zram[0x1100];
+ diff = end - start;
+ if (pal)
+ expect_range(ok, diff, 0xf4, 0xf6);
+ else
+ expect_range(ok, diff, 0x27, 0x29);
+ write8(&z80[0x4001], 0); // stop, but should keep the flag
+ mem_barrier();
+ burn10(32*6/10); // busy bit, 32 FM ticks (M/7/6)
+ if (is_b) {
+ expect(ok, z80[0x4000], 2);
+ write8(&z80[0x4001], 0x20); // reset flag (reg 0x27, set up by z80)
+ }
+ else {
+ expect(ok, z80[0x4000], 1);
+ write8(&z80[0x4001], 0x10);
+ }
+ mem_barrier();
+ burn10(32*6/10);
+ expect(ok, z80[0x4000], 0);
+ return ok;
+}
+
+static int t_tim_ym_timera_z80(void)
+{
+ return t_tim_ym_timer_z80(0);
+}
+
+static int t_tim_ym_timerb_z80(void)
+{
+ return t_tim_ym_timer_z80(1);
+}
+
+static int t_tim_ym_timerb_stop(void)
+{
+ const struct {
+ //u8 vcnt_start;
+ //u8 hcnt_start;
+ u16 vcnt_start;
+ u16 stat0;
+ //u8 vcnt_end;
+ //u8 hcnt_end;
+ u16 vcnt_end;
+ u16 stat1;
+ } *t = (void *)0xfff000;
+ u8 *z80 = (u8 *)0xa00000;
+ u16 diff;
+ int ok = 1;
+ write16(0xa11100, 0x100);
+ while (read16(0xa11100) & 0x100)
+ ;
+ test_ym_stopped_tick();
+ mem_barrier();
+ //start = ((u16)t->vcnt_start << 8) | hcnt2tm[t->hcnt_start >> 4];
+ //end = ((u16)t->vcnt_end << 8) | hcnt2tm[t->hcnt_end >> 4];
+ //diff = end - start;
+ diff = t->vcnt_end - t->vcnt_start;
+ //expect_range(ok, diff, 0x492, 0x5c2); // why so much variation?
+ expect_range(ok, diff, 4, 5);
+ expect(ok, t->stat0, 0);
+ expect(ok, t->stat1, 2);
+ expect(ok, z80[0x4000], 2);
+ write8(&z80[0x4001], 0x30);
+ return ok;
+}
+
+static int t_tim_ym_timer_ab_sync(void)
+{
+ u16 v = test_ym_ab_sync();
+ int ok = 1;
+ expect(ok, v, 3);
+ return ok;
+}
+
+struct irq_test {
+ u16 cnt;
+ union {
+ u16 hv;
+ u8 v;
+ } first, last;
+ u16 pad;
+};
+
+// broken on fresh boot due to uknown reasons
+static int t_irq_hint(void)
+{
+ struct irq_test *it = (void *)0xfff000;
+ struct irq_test *itv = it + 1;
+ int ok = 1;
+
+ memset_(it, 0, sizeof(*it) * 2);
+ memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
+ memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
+
+ // without this, tests fail after cold boot
+ while (!(read16(VDP_CTRL_PORT) & 8))
+ /* not blanking */;
+
+ // for more fun, disable the display
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
+
+ VDP_setReg(10, 0);
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ while (read8(VDP_HV_COUNTER) != 229)
+ ;
+ // take the pending irq
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
+ move_sr(0x2000);
+ burn10(488 * 2 / 10);
+ move_sr(0x2700);
+ expect(ok, it->first.v, 229); // pending irq trigger
+ expect(ok, it->cnt, 1);
+ expect(ok, itv->cnt, 0);
+
+ // count irqs
+ it->cnt = it->first.hv = it->last.hv = 0;
+ move_sr(0x2000);
+ while (read8(VDP_HV_COUNTER) != 4)
+ ;
+ while (read8(VDP_HV_COUNTER) != 228)
+ ;
+ move_sr(0x2700);
+ expect(ok, it->cnt, 225);
+ expect(ok, it->first.v, 0);
+ expect(ok, it->last.v, 224);
+
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+
+ // detect reload line
+ it->cnt = it->first.hv = it->last.hv = 0;
+ VDP_setReg(10, 17);
+ move_sr(0x2000);
+ while (read16(VDP_CTRL_PORT) & 8)
+ /* blanking */;
+ VDP_setReg(10, 255);
+ while (read8(VDP_HV_COUNTER) != 228)
+ ;
+ move_sr(0x2700);
+ expect(ok, it->cnt, 1);
+ expect(ok, it->first.v, 17);
+ expect(ok, it->last.v, 17);
+
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
+
+ return ok;
+}
+
+static int t_irq_both_cpu_unmask(void)
+{
+ struct irq_test *ith = (void *)0xfff000;
+ struct irq_test *itv = ith + 1;
+ u16 s0, s1;
+ int ok = 1;
+
+ memset_(ith, 0, sizeof(*ith) * 2);
+ memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
+ memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
+ VDP_setReg(10, 0);
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ while (read8(VDP_HV_COUNTER) != 226)
+ ;
+ VDP_setReg(10, 99);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
+ /* go to active display line 100 */
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ s0 = read16(VDP_CTRL_PORT);
+ s1 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
+ move_sr(0x2700);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+
+ expect(ok, itv->cnt, 1); // vint count
+ expect(ok, itv->first.v, 100); // vint line
+ expect(ok, ith->cnt, 1); // hint count
+ expect(ok, ith->first.v, 100); // hint line
+ expect_bits(ok, s0, SR_F, SR_F);
+ expect_bits(ok, s1, 0, SR_F);
+ return ok;
+}
+
+static int t_irq_ack_v_h(void)
+{
+ struct irq_test *ith = (void *)0xfff000;
+ struct irq_test *itv = ith + 1;
+ u16 s0, s1, s2;
+ int ok = 1;
+
+ memset_(ith, 0, sizeof(*ith) * 2);
+ memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
+ memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
+ VDP_setReg(10, 0);
+ /* ensure hcnt reload */
+ while (!(read16(VDP_CTRL_PORT) & 8))
+ /* not blanking */;
+ while (read16(VDP_CTRL_PORT) & 8)
+ /* blanking */;
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0);
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ while (read8(VDP_HV_COUNTER) != 226)
+ ;
+ s0 = read16(VDP_CTRL_PORT);
+ s1 = move_sr_and_read(0x2500, VDP_CTRL_PORT);
+ burn10(666 / 10);
+ s2 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
+ burn10(488 / 10);
+ move_sr(0x2700);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+
+ expect(ok, itv->cnt, 1); // vint count
+ expect(ok, itv->first.v, 226); // vint line
+ expect(ok, ith->cnt, 1); // hint count
+ expect(ok, ith->first.v, 228); // hint line
+ expect_bits(ok, s0, SR_F, SR_F);
+ expect_bits(ok, s1, 0, SR_F);
+ expect_bits(ok, s2, 0, SR_F);
+ return ok;
+}
+
+static int t_irq_ack_v_h_2(void)
+{
+ struct irq_test *ith = (void *)0xfff000;
+ struct irq_test *itv = ith + 1;
+ u16 s0, s1;
+ int ok = 1;
+
+ memset_(ith, 0, sizeof(*ith) * 2);
+ memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
+ memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
+ VDP_setReg(10, 0);
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ while (read8(VDP_HV_COUNTER) != 226)
+ ;
+ s0 = read16(VDP_CTRL_PORT);
+ test_v_h_2();
+ s1 = read16(VDP_CTRL_PORT);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+
+ expect(ok, itv->cnt, 2); // vint count
+ expect(ok, itv->first.v, 226); // vint line
+ expect(ok, ith->cnt, 1); // hint count
+ expect(ok, ith->first.v, 227); // hint line
+ expect_bits(ok, s0, SR_F, SR_F);
+ expect_bits(ok, s1, 0, SR_F);
+ return ok;
+}
+
+static int t_irq_ack_h_v(void)
+{
+ u16 *ram = (u16 *)0xfff000;
+ u8 *ram8 = (u8 *)0xfff000;
+ u16 s0, s1, s[4];
+ int ok = 1;
+
+ ram[0] = ram[1] = ram[2] =
+ ram[4] = ram[5] = ram[6] = 0;
+ memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
+ memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
+ VDP_setReg(10, 0);
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ while (read8(VDP_HV_COUNTER) != 226)
+ ;
+ s0 = read16(VDP_CTRL_PORT);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
+ move_sr(0x2000);
+ burn10(666 / 10);
+ s1 = read16(VDP_CTRL_PORT);
+ write_and_read1(VDP_CTRL_PORT, 0x8000 | (VDP_MODE2 << 8)
+ | VDP_MODE2_MD | VDP_MODE2_IE0, s);
+ move_sr(0x2700);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+
+ expect(ok, ram[0], 1); // hint count
+ expect(ok, ram8[2], 226); // hint line
+ expect(ok, ram[4], 1); // vint count
+ expect(ok, ram8[10], 228); // vint line
+ expect_bits(ok, s0, SR_F, SR_F);
+ expect_bits(ok, s1, SR_F, SR_F);
+ expect_bits(ok, s[0], SR_F, SR_F);
+ expect_bits(ok, s[1], SR_F, SR_F);
+ expect_bits(ok, s[2], 0, SR_F);
+ expect_bits(ok, s[3], 0, SR_F);
+ return ok;
+}
+
+static int t_irq_ack_h_v_2(void)
+{
+ u16 *ram = (u16 *)0xfff000;
+ u8 *ram8 = (u8 *)0xfff000;
+ u16 s0, s1;
+ int ok = 1;
+
+ ram[0] = ram[1] = ram[2] =
+ ram[4] = ram[5] = ram[6] = 0;
+ memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
+ memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
+ VDP_setReg(10, 0);
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ while (read8(VDP_HV_COUNTER) != 226)
+ ;
+ s0 = read16(VDP_CTRL_PORT);
+ test_h_v_2();
+ s1 = read16(VDP_CTRL_PORT);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+
+ expect(ok, ram[0], 2); // hint count
+ expect(ok, ram8[2], 226); // hint first line
+ expect(ok, ram8[4], 226); // hint last line
+ expect(ok, ram[4], 0); // vint count
+ expect(ok, ram8[10], 0); // vint line
+ expect_bits(ok, s0, SR_F, SR_F);
+ expect_bits(ok, s1, 0, SR_F);
+ return ok;
+}
+
+static void t_irq_f_flag(void)
+{
+ memcpy_((void *)0xff0140, test_f_vint, test_f_vint_end - test_f_vint);
+ memset_((void *)0xff0000, 0, 10);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
+ test_f();
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+}
+
+static int t_irq_f_flag_h40(void)
+{
+ u8 f, *r = (u8 *)0xff0000;
+ int ok = 1;
+
+ t_irq_f_flag();
+
+ expect_bits(ok, r[0], 0, SR_F);
+ expect_bits(ok, r[1], 0, SR_F);
+ expect_bits(ok, r[2], 0, SR_F);
+ // hits 1-3 times in range 3-9, usually ~5
+ f = r[3] | r[4] | r[5] | r[6] | r[7];
+
+ expect_bits(ok, r[10], 0, SR_F);
+ expect_bits(ok, r[11], 0, SR_F);
+ expect_bits(ok, f, SR_F, SR_F);
+ return ok;
+}
+
+static int t_irq_f_flag_h32(void)
+{
+ u8 f, *r = (u8 *)0xff0000;
+ int ok = 1;
+
+ VDP_setReg(VDP_MODE4, 0x00);
+ t_irq_f_flag();
+ VDP_setReg(VDP_MODE4, 0x81);
+
+ expect_bits(ok, r[0], 0, SR_F);
+ expect_bits(ok, r[1], 0, SR_F);
+ // hits 1-3 times in range 2-7, usually 3
+ f = r[2] | r[3] | r[4] | r[5] | r[6] | r[7];
+
+ expect_bits(ok, r[8], 0, SR_F);
+ expect_bits(ok, r[9], 0, SR_F);
+ expect_bits(ok, r[10], 0, SR_F);
+ expect_bits(ok, r[11], 0, SR_F);
+ expect_bits(ok, f, SR_F, SR_F);
+ return ok;
+}
+
+// 32X
+
+static int t_32x_init(void)
+{
+ void (*do_32x_enable)(void) = (void *)0xff0040;
+ u32 M_OK = MKLONG('M','_','O','K');
+ u32 S_OK = MKLONG('S','_','O','K');
+ u32 *r = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r;
+ int i, ok = 1;
+
+ //v1070 = read32(0x1070);
+
+ /* what does REN mean exactly?
+ * Seems to be sometimes clear after reset */
+ for (i = 0; i < 1000000; i++)
+ if (read16(r16) & 0x80)
+ break;
+ expect(ok, r16[0x00/2], 0x82);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 0);
+ expect(ok, r16[0x06/2], 0);
+ expect(ok, r[0x14/4], 0);
+ expect(ok, r[0x18/4], 0);
+ expect(ok, r[0x1c/4], 0);
+ write32(&r[0x20/4], 0); // master resp
+ write32(&r[0x24/4], 0); // slave resp
+ write32(&r[0x28/4], 0);
+ write32(&r[0x2c/4], 0);
+
+ // could just set RV, but BIOS reads ROM, so can't
+ memcpy_(do_32x_enable, x32x_enable,
+ x32x_enable_end - x32x_enable);
+ do_32x_enable();
+
+ expect(ok, r16[0x00/2], 0x83);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 0);
+ expect(ok, r16[0x06/2], 1); // RV
+ expect(ok, r[0x14/4], 0);
+ expect(ok, r[0x18/4], 0);
+ expect(ok, r[0x1c/4], 0);
+ expect(ok, r[0x20/4], M_OK);
+ while (!read16(&r16[0x24/2]))
+ ;
+ expect(ok, r[0x24/4], S_OK);
+ write32(&r[0x20/4], 0);
+ return ok;
+}
+
+static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
+{
+ u16 v, *r = (u16 *)0xa15120;
+ u16 cmd_s = cmd | (is_slave << 15);
+ int i;
+
+ write32(&r[4/2], a0);
+ write32(&r[8/2], a1);
+ mem_barrier();
+ write16(r, cmd_s);
+ mem_barrier();
+ for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
+ burn10(1);
+ if (v != 0) {
+ printf("cmd clr: %x\n", v);
+ mem_barrier();
+ printf("c, e: %02x %02x\n", r[0x0c/2], r[0x0e/2]);
+ write16(r, 0);
+ }
+ v = read16(&r[1]);
+ if (v != 0) {
+ printf("cmd err: %x\n", v);
+ write16(&r[1], 0);
+ }
+}
+
+static int t_32x_echo(void)
+{
+ u16 *r = (u16 *)0xa15120;
+ int ok = 1;
+
+ x32_cmd(CMD_ECHO, 0x12340000, 0, 0);
+ expect(ok, r[0x06/2], 0x1234);
+ x32_cmd(CMD_ECHO, 0x23450000, 0, 1);
+ expect(ok, r[0x06/2], 0xa345);
+ return ok;
+}
+
+static int t_32x_md_bios(void)
+{
+ void (*do_call_c0)(int a, int d) = (void *)0xff0040;
+ u8 *rmb = (u8 *)0xff0000;
+ u32 *rl = (u32 *)0;
+ int ok = 1;
+
+ memcpy_(do_call_c0, test_32x_b_c0,
+ test_32x_b_c0_end - test_32x_b_c0);
+ write8(rmb, 0);
+ do_call_c0(0xff0000, 0x5a);
+
+ expect(ok, rmb[0], 0x5a);
+ expect(ok, rl[0x04/4], 0x880200);
+ expect(ok, rl[0x10/4], 0x880212);
+ expect(ok, rl[0x94/4], 0x8802d8);
+ return ok;
+}
+
+static int t_32x_md_rom(void)
+{
+ u32 *rl = (u32 *)0;
+ int ok = 1;
+
+ expect(ok, rl[0x004/4], 0x880200);
+ expect(ok, rl[0x100/4], 0x53454741);
+ expect(ok, rl[0x70/4], 0);
+ write32(&rl[0x70/4], 0xa5123456);
+ write32(&rl[0x78/4], ~0);
+ mem_barrier();
+ expect(ok, rl[0x78/4], 0x8802ae);
+ expect(ok, rl[0x70/4], 0xa5123456);
+ //expect(ok, rl[0x1070/4], v1070);
+ write32(&rl[0x70/4], 0);
+ // with RV 0x880000/0x900000 hangs, can't test
+ return ok;
+}
+
+static int t_32x_md_fb(void)
+{
+ u8 *fbb = (u8 *)0x840000;
+ u16 *fbw = (u16 *)fbb;
+ u32 *fbl = (u32 *)fbb;
+ u8 *fob = (u8 *)0x860000;
+ u16 *fow = (u16 *)fob;
+ u32 *fol = (u32 *)fob;
+ int ok = 1;
+
+ fbl[0] = 0x12345678;
+ fol[1] = 0x89abcdef;
+ mem_barrier();
+ expect(ok, fbw[1], 0x5678);
+ expect(ok, fow[2], 0x89ab);
+ fbb[0] = 0;
+ fob[1] = 0;
+ fbw[1] = 0;
+ fow[2] = 0;
+ fow[3] = 1;
+ mem_barrier();
+ fow[3] = 0x200;
+ mem_barrier();
+ expect(ok, fol[0], 0x12340000);
+ expect(ok, fbl[1], 0x89ab0201);
+ return ok;
+}
+
+static int t_32x_sh_fb(void)
+{
+ u32 *fbl = (u32 *)0x840000;
+ int ok = 1;
+
+ fbl[0] = 0x12345678;
+ fbl[1] = 0x89abcdef;
+ mem_barrier();
+ write8(0xa15100, 0x80); // FM=1
+ x32_cmd(CMD_WRITE8, 0x24000000, 0, 0);
+ x32_cmd(CMD_WRITE8, 0x24020001, 0, 0);
+ x32_cmd(CMD_WRITE16, 0x24000002, 0, 0);
+ x32_cmd(CMD_WRITE16, 0x24020000, 0, 0);
+ x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1);
+ write8(0xa15100, 0x00); // FM=0
+ mem_barrier();
+ expect(ok, fbl[0], 0x12340000);
+ expect(ok, fbl[1], 0x5aabcda5);
+ return ok;
+}
+
+static int t_32x_disable(void)
+{
+ void (*do_32x_disable)(void) = (void *)0xff0040;
+ u32 *r = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r;
+ u32 *rl = (u32 *)0;
+ int ok = 1;
+
+ expect(ok, r16[0x00/2], 0x83);
+
+ memcpy_(do_32x_disable, x32x_disable,
+ x32x_disable_end - x32x_disable);
+ do_32x_disable();
+
+ expect(ok, r16[0x00/2], 0x82);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 0);
+ expect(ok, r16[0x06/2], 1); // RV
+ expect(ok, r[0x14/4], 0);
+ expect(ok, r[0x18/4], 0);
+ expect(ok, r[0x1c/4], 0);
+ expect(ok, rl[0x04/4], 0x000800);
+
+ write16(&r16[0x06/2], 0); // can just set without ADEN
+ mem_barrier();
+ expect(ok, r16[0x06/2], 0); // RV
+ return ok;
+}
+
+enum {
+ T_MD = 0,
+ T_32 = 1, // 32X
+};
+