+RST:\r
+ andi.b #0x0F, (0xA10001) /* 24 */\r
+ bne.s 0f /* 10 */\r
+ move.w #0x8104, (0xc00004)\r
+ bra 1f\r
+0:\r
+ move.l #0x53454741, (0xA14000) /* 28 'SEGA' */\r
+1:\r
+ move.w (0xc00008), %d0 /* 16 */\r
+ move.w %d0, -(%sp)\r
+ subq.l #2, %sp\r
+ move %sp, %usp\r
+\r
+ move.w #0x2600, %sr\r
+\r
+ /* clear .bss */\r
+ moveq.l #0, %d0\r
+ lea __bss_start, %a0\r
+ lea __end, %a1\r
+0:\r
+ move.l %d0, (%a0)+\r
+ cmp.l %a1, %a0\r
+ blt.s 0b\r
+\r
+# move.w #0x2000, %sr\r
+ jsr main\r
+0:\r
+ bra 0b\r
+\r
+#HBL:\r
+#VBL:\r
+# rte\r
+\r
+RST32X:\r
+ lea ram_rv_switch, %a0\r
+ movea.l #0xff0100, %a1\r
+ lea ram_rv_switch_end, %a2\r
+0:\r
+ move.l (%a0)+, (%a1)+\r
+ cmp.l %a2, %a0\r
+ blt.s 0b\r
+ jmp (0xff0100).l\r
+\r
+ram_rv_switch:\r
+ move.l (0x880004).l, %a0\r
+ bset #0, (0xa15107).l /* RV=1 */\r
+ nop /* just in case */\r
+ jmp (%a0)\r
+ram_rv_switch_end:\r
+\r
+pre_exception:\r
+ move.w #0x2700, %sr\r
+ movem.l %d0-%d7/%a0-%a7,-(%sp)\r
+ add.w #2, 0x3e(%sp) /* ecxnum */\r
+ move.l %sp, %d0\r
+ move.l %d0,-(%sp) /* arg0 */\r
+ jsr exception\r
+0:\r
+ bra 0b\r
+\r
+.macro exc_stub num\r
+exc\num:\r
+ move.w #0x\num, -(%sp)\r
+ bra pre_exception\r
+.endm\r
+\r
+exc_stub 02\r
+exc_stub 03\r
+exc_stub 04\r
+exc_stub 05\r
+exc_stub 06\r
+exc_stub 07\r
+exc_stub 08\r
+exc_stub 09\r
+exc_stub 0a\r
+exc_stub 0b\r
+exc_stub 0c\r
+exc_stub 0d\r
+exc_stub 0e\r
+exc_stub 0f\r
+\r
+exc_stub 10\r
+exc_stub 11\r
+exc_stub 12\r
+exc_stub 13\r
+exc_stub 14\r
+exc_stub 15\r
+exc_stub 16\r
+exc_stub 17\r
+exc_stub 18\r
+exc_stub 19\r
+exc_stub 1a\r
+exc_stub 1b\r
+HBL:\r
+exc_stub 1c\r
+exc_stub 1d\r
+VBL:\r
+exc_stub 1e\r
+exc_stub 1f\r
+\r