// For commercial use, separate licencing terms must be obtained.\r
\r
\r
-//#define __debug_io\r
+#define __debug_io\r
\r
#include "PicoInt.h"\r
\r
-#include "sound/sound.h"\r
#include "sound/ym2612.h"\r
#include "sound/sn76496.h"\r
\r
+#ifndef UTYPES_DEFINED\r
typedef unsigned char u8;\r
typedef unsigned short u16;\r
typedef unsigned int u32;\r
+#define UTYPES_DEFINED\r
+#endif\r
\r
extern unsigned int lastSSRamWrite; // used by serial SRAM code\r
\r
#ifdef _ASM_MEMORY_C\r
-u8 PicoRead8(u32 a);\r
-u16 PicoRead16(u32 a);\r
+u32 PicoRead8(u32 a);\r
+u32 PicoRead16(u32 a);\r
+void PicoWrite8(u32 a,u8 d);\r
void PicoWriteRomHW_SSF2(u32 a,u32 d);\r
void PicoWriteRomHW_in1 (u32 a,u32 d);\r
#endif\r
extern unsigned int ppop;\r
#endif\r
\r
-#if defined(EMU_C68K) || defined(EMU_A68K)\r
+#ifdef IO_STATS\r
+void log_io(unsigned int addr, int bits, int rw);\r
+#else\r
+#define log_io(...)\r
+#endif\r
+\r
+#if defined(EMU_C68K)\r
static __inline int PicoMemBase(u32 pc)\r
{\r
int membase=0;\r
#endif\r
\r
\r
-#ifdef EMU_A68K\r
-extern u8 *OP_ROM=NULL,*OP_RAM=NULL;\r
-#endif\r
-\r
-static u32 CPU_CALL PicoCheckPc(u32 pc)\r
+static u32 PicoCheckPc(u32 pc)\r
{\r
u32 ret=0;\r
#if defined(EMU_C68K)\r
- pc-=PicoCpu.membase; // Get real pc\r
- pc&=0xfffffe;\r
-\r
- PicoCpu.membase=PicoMemBase(pc);\r
+ pc-=PicoCpuCM68k.membase; // Get real pc\r
+// pc&=0xfffffe;\r
+ pc&=~1;\r
+ if ((pc<<8) == 0)\r
+ {\r
+ printf("%i:%03i: game crash detected @ %06x\n", Pico.m.frame_count, Pico.m.scanline, SekPc);\r
+ return (int)Pico.rom + Pico.romsize; // common crash condition, can happen if acc timing is off\r
+ }\r
\r
- ret = PicoCpu.membase+pc;\r
-#elif defined(EMU_A68K)\r
- OP_ROM=(u8 *)PicoMemBase(pc);\r
+ PicoCpuCM68k.membase=PicoMemBase(pc&0x00ffffff);\r
+ PicoCpuCM68k.membase-=pc&0xff000000;\r
\r
- // don't bother calling us back unless it's outside the 64k segment\r
- M68000_regs.AsmBank=(pc>>16);\r
+ ret = PicoCpuCM68k.membase+pc;\r
#endif\r
return ret;\r
}\r
\r
\r
-int PicoInitPc(u32 pc)\r
+PICO_INTERNAL int PicoInitPc(u32 pc)\r
{\r
PicoCheckPc(pc);\r
return 0;\r
}\r
\r
#ifndef _ASM_MEMORY_C\r
-void PicoMemReset()\r
+PICO_INTERNAL_ASM void PicoMemReset(void)\r
{\r
}\r
#endif\r
\r
// -----------------------------------------------------------------\r
\r
-#ifndef _ASM_MEMORY_C\r
-// address must already be checked\r
-static int SRAMRead(u32 a)\r
-{\r
- u8 *d = SRam.data-SRam.start+a;\r
- return (d[0]<<8)|d[1];\r
-}\r
-#endif\r
-\r
-static int PadRead(int i)\r
+int PadRead(int i)\r
{\r
- int pad=0,value=0,TH;\r
+ int pad,value,data_reg;\r
pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU\r
- TH=Pico.ioports[i+1]&0x40;\r
+ data_reg=Pico.ioports[i+1];\r
+\r
+ // orr the bits, which are set as output\r
+ value = data_reg&(Pico.ioports[i+4]|0x80);\r
\r
if(PicoOpt & 0x20) { // 6 button gamepad enabled\r
int phase = Pico.m.padTHPhase[i];\r
\r
- if(phase == 2 && !TH) {\r
- value=(pad&0xc0)>>2; // ?0SA 0000\r
- goto end;\r
- } else if(phase == 3 && TH) {\r
- value=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ\r
- goto end;\r
- } else if(phase == 3 && !TH) {\r
- value=((pad&0xc0)>>2)|0x0f; // ?0SA 1111\r
- goto end;\r
+ if(phase == 2 && !(data_reg&0x40)) { // TH\r
+ value|=(pad&0xc0)>>2; // ?0SA 0000\r
+ return value;\r
+ } else if(phase == 3) {\r
+ if(data_reg&0x40)\r
+ value|=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ\r
+ else\r
+ value|=((pad&0xc0)>>2)|0x0f; // ?0SA 1111\r
+ return value;\r
}\r
}\r
\r
- if(TH) value=(pad&0x3f); // ?1CB RLDU\r
- else value=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU\r
+ if(data_reg&0x40) // TH\r
+ value|=(pad&0x3f); // ?1CB RLDU\r
+ else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU\r
\r
- end:\r
+ return value; // will mirror later\r
+}\r
\r
- // orr the bits, which are set as output\r
- value |= Pico.ioports[i+1]&Pico.ioports[i+4];\r
\r
- return value; // will mirror later\r
+#ifndef _ASM_MEMORY_C\r
+static\r
+#endif\r
+u32 SRAMRead(u32 a)\r
+{\r
+ unsigned int sreg = Pico.m.sram_reg;\r
+ if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM\r
+ elprintf(EL_SRAMIO, "normal sram detected.");\r
+ Pico.m.sram_reg|=0x10; // should be normal SRAM\r
+ }\r
+ if(sreg & 4) // EEPROM read\r
+ return SRAMReadEEPROM();\r
+ else // if(sreg & 1) // (sreg&5) is one of prerequisites\r
+ return *(u8 *)(SRam.data-SRam.start+a);\r
}\r
\r
-u8 z80Read8(u32 a)\r
+static void SRAMWrite(u32 a, u32 d)\r
{\r
- if(Pico.m.z80Run&1) return 0;\r
-\r
- a&=0x1fff;\r
-\r
- if(!(PicoOpt&4)) {\r
- // Z80 disabled, do some faking\r
- static u8 zerosent = 0;\r
- if(a == Pico.m.z80_lastaddr) { // probably polling something\r
- u8 d = Pico.m.z80_fakeval;\r
- if((d & 0xf) == 0xf && !zerosent) {\r
- d = 0; zerosent = 1;\r
- } else {\r
- Pico.m.z80_fakeval++;\r
- zerosent = 0;\r
- }\r
- return d;\r
+ unsigned int sreg = Pico.m.sram_reg;\r
+ if(!(sreg & 0x10)) {\r
+ // not detected SRAM\r
+ if((a&~1)==0x200000) {\r
+ elprintf(EL_SRAMIO, "eeprom detected.");\r
+ sreg|=4; // this should be a game with EEPROM (like NBA Jam)\r
+ SRam.start=0x200000; SRam.end=SRam.start+1;\r
+ } else\r
+ elprintf(EL_SRAMIO, "normal sram detected.");\r
+ sreg|=0x10;\r
+ Pico.m.sram_reg=sreg;\r
+ }\r
+ if(sreg & 4) { // EEPROM write\r
+ // this diff must be at most 16 for NBA Jam to work\r
+ if(SekCyclesDoneT()-lastSSRamWrite < 16) {\r
+ // just update pending state\r
+ elprintf(EL_EEPROM, "eeprom: skip because cycles=%i", SekCyclesDoneT()-lastSSRamWrite);\r
+ SRAMUpdPending(a, d);\r
} else {\r
- Pico.m.z80_fakeval = 0;\r
+ int old=sreg;\r
+ SRAMWriteEEPROM(sreg>>6); // execute pending\r
+ SRAMUpdPending(a, d);\r
+ if ((old^Pico.m.sram_reg)&0xc0) // update time only if SDA/SCL changed\r
+ lastSSRamWrite = SekCyclesDoneT();\r
+ }\r
+ } else if(!(sreg & 2)) {\r
+ u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
+ if(*pm != (u8)d) {\r
+ SRam.changed = 1;\r
+ *pm=(u8)d;\r
}\r
}\r
-\r
- Pico.m.z80_lastaddr = (u16) a;\r
- return Pico.zram[a];\r
}\r
\r
-\r
// for nonstandard reads\r
#ifndef _ASM_MEMORY_C\r
static\r
#endif\r
-u32 UnusualRead16(u32 a, int realsize)\r
+u32 OtherRead16End(u32 a, int realsize)\r
{\r
u32 d=0;\r
\r
- dprintf("strange r%i: %06x @%06x", realsize, a&0xffffff, SekPc);\r
-\r
// for games with simple protection devices, discovered by Haze\r
// some dumb detection is used, but that should be enough to make things work\r
if ((a>>22) == 1 && Pico.romsize >= 512*1024) {\r
}\r
\r
end:\r
- dprintf("ret = %04x", d);\r
+ elprintf(EL_UIO, "strange r%i: [%06x] %04x @%06x", realsize, a&0xffffff, d, SekPc);\r
return d;\r
}\r
\r
-#ifndef _ASM_MEMORY_C\r
-static\r
-#endif\r
-u32 OtherRead16(u32 a, int realsize)\r
-{\r
- u32 d=0;\r
-\r
- if ((a&0xff0000)==0xa00000) {\r
- if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)\r
- if ((a&0x6000)==0x4000) { if(PicoOpt&1) d=YM2612Read(); else d=Pico.m.rotate++&3; dprintf("read ym2612: %04x", d); goto end; } // 0x4000-0x5fff, Fudge if disabled\r
- d=0xffff; goto end;\r
- }\r
- if ((a&0xffffe0)==0xa10000) { // I/O ports\r
- a=(a>>1)&0xf;\r
- switch(a) {\r
- case 0: d=Pico.m.hardware; break; // Hardware value (Version register)\r
- case 1: d=PadRead(0); d|=Pico.ioports[1]&0x80; break;\r
- case 2: d=PadRead(1); d|=Pico.ioports[2]&0x80; break;\r
- default: d=Pico.ioports[a]; break; // IO ports can be used as RAM\r
- }\r
- d|=d<<8;\r
- goto end;\r
- }\r
- // |=0x80 for Shadow of the Beast & Super Offroad; rotate fakes next fetched instruction for Time Killers\r
- if (a==0xa11100) {\r
- d=Pico.m.z80Run&1;\r
-#if 0\r
- if (!d) {\r
- // do we need this?\r
- extern int z80stopCycle; // TODO: tidy\r
- int stop_before = SekCyclesDone() - z80stopCycle;\r
- if (stop_before > 0 && stop_before <= 16) // Gens uses 16 here\r
- d = 1; // bus not yet available\r
- }\r
-#endif\r
- d=(d<<8)|0x8000|Pico.m.rotate++;\r
- dprintf("get_zrun: %04x [%i|%i] @%06x", d, Pico.m.scanline, SekCyclesDone(), SekPc);\r
- goto end; }\r
-\r
-#ifndef _ASM_MEMORY_C\r
- if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }\r
-#endif\r
-\r
- d = UnusualRead16(a, realsize);\r
-\r
-end:\r
- return d;\r
-}\r
\r
//extern UINT32 mz80GetRegisterValue(void *, UINT32);\r
\r
-static void OtherWrite8(u32 a,u32 d,int realsize)\r
+static void OtherWrite8End(u32 a,u32 d,int realsize)\r
{\r
- if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound\r
- if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram\r
- if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound\r
- if ((a&0xffffe0)==0xa10000) { // I/O ports\r
- a=(a>>1)&0xf;\r
- // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r
- if(PicoOpt&0x20) {\r
- if(a==1) {\r
- Pico.m.padDelay[0] = 0;\r
- if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;\r
- }\r
- else if(a==2) {\r
- Pico.m.padDelay[1] = 0;\r
- if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;\r
- }\r
- }\r
- Pico.ioports[a]=(u8)d; // IO ports can be used as RAM\r
- return;\r
- }\r
- if (a==0xa11100) {\r
- extern int z80startCycle, z80stopCycle;\r
- //int lineCycles=(488-SekCyclesLeft)&0x1ff;\r
- d&=1; d^=1;\r
- if(!d) {\r
- // this is for a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)\r
- if (Pico.m.z80Run) {\r
- int lineCycles=(488-SekCyclesLeft)&0x1ff;\r
- z80stopCycle = SekCyclesDone();\r
- lineCycles=(lineCycles>>1)-(lineCycles>>5);\r
- z80_run(lineCycles);\r
- }\r
- } else {\r
- z80startCycle = SekCyclesDone();\r
- //if(Pico.m.scanline != -1)\r
- }\r
- dprintf("set_zrun: %02x [%i|%i] @%06x", d, Pico.m.scanline, SekCyclesDone(), /*mz80GetRegisterValue(NULL, 0),*/ SekPc);\r
- Pico.m.z80Run=(u8)d; return;\r
- }\r
- if (a==0xa11200) { dprintf("write z80Reset: %02x", d); if(!(d&1)) z80_reset(); return; }\r
-\r
- if ((a&0xff7f00)==0xa06000) // Z80 BANK register\r
- {\r
- Pico.m.z80_bank68k>>=1;\r
- Pico.m.z80_bank68k|=(d&1)<<8;\r
- Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one\r
- return;\r
- }\r
-\r
- if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)(d|(d<<8))); return; } // Byte access gets mirrored\r
-\r
// sram\r
- //if(a==0x200000) dprintf("cc : %02x @ %06x [%i|%i]", d, SekPc, SekCyclesDoneT(), SekCyclesDone());\r
- //if(a==0x200001) dprintf("w8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT());\r
if(a >= SRam.start && a <= SRam.end) {\r
- unsigned int sreg = Pico.m.sram_reg;\r
- if(!(sreg & 0x10)) {\r
- // not detected SRAM\r
- if((a&~1)==0x200000) {\r
- Pico.m.sram_reg|=4; // this should be a game with EEPROM (like NBA Jam)\r
- SRam.start=0x200000; SRam.end=SRam.start+1;\r
- }\r
- Pico.m.sram_reg|=0x10;\r
- }\r
- if(sreg & 4) { // EEPROM write\r
- if(SekCyclesDoneT()-lastSSRamWrite < 46) {\r
- // just update pending state\r
- SRAMUpdPending(a, d);\r
- } else {\r
- SRAMWriteEEPROM(sreg>>6); // execute pending\r
- SRAMUpdPending(a, d);\r
- lastSSRamWrite = SekCyclesDoneT();\r
- }\r
- } else if(!(sreg & 2)) {\r
- u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
- if(*pm != (u8)d) {\r
- SRam.changed = 1;\r
- *pm=(u8)d;\r
- }\r
- }\r
+ elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d, SekPc);\r
+ SRAMWrite(a, d);\r
return;\r
}\r
\r
#else\r
// sram access register\r
if(a == 0xA130F1) {\r
- Pico.m.sram_reg = (u8)(d&3);\r
+ elprintf(EL_SRAMIO, "sram reg=%02x", d);\r
+ Pico.m.sram_reg &= ~3;\r
+ Pico.m.sram_reg |= (u8)(d&3);\r
return;\r
}\r
#endif\r
- dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
+ elprintf(EL_UIO, "strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
\r
if(a >= 0xA13004 && a < 0xA13040) {\r
// dumb 12-in-1 or 4-in-1 banking support\r
Pico.m.prot_bytes[(a>>2)&1] = (u8)d;\r
}\r
\r
-static void OtherWrite16(u32 a,u32 d)\r
-{\r
- if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }\r
- if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)\r
-\r
- if ((a&0xffffe0)==0xa10000) { // I/O ports\r
- a=(a>>1)&0xf;\r
- // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r
- if(PicoOpt&0x20) {\r
- if(a==1) {\r
- Pico.m.padDelay[0] = 0;\r
- if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;\r
- }\r
- else if(a==2) {\r
- Pico.m.padDelay[1] = 0;\r
- if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;\r
- }\r
- }\r
- Pico.ioports[a]=(u8)d; // IO ports can be used as RAM\r
- return;\r
- }\r
- if (a==0xa11100) { OtherWrite8(a, d>>8, 16); return; }\r
- if (a==0xa11200) { dprintf("write z80reset: %04x", d); if(!(d&0x100)) z80_reset(); return; }\r
\r
- OtherWrite8(a, d>>8, 16);\r
- OtherWrite8(a+1,d&0xff, 16);\r
-}\r
+#include "MemoryCmn.c"\r
+\r
\r
// -----------------------------------------------------------------\r
// Read Rom and read Ram\r
\r
#ifndef _ASM_MEMORY_C\r
-u8 CPU_CALL PicoRead8(u32 a)\r
+PICO_INTERNAL_ASM u32 PicoRead8(u32 a)\r
{\r
u32 d=0;\r
\r
\r
#if !(defined(EMU_C68K) && defined(EMU_M68K))\r
// sram\r
- if(a >= SRam.start && a <= SRam.end) {\r
- unsigned int sreg = Pico.m.sram_reg;\r
- if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM\r
- Pico.m.sram_reg|=0x10; // should be normal SRAM\r
- }\r
- if(sreg & 4) { // EEPROM read\r
- d = SRAMReadEEPROM();\r
- goto end;\r
- } else if(sreg & 1) {\r
- d = *(u8 *)(SRam.data-SRam.start+a);\r
- goto end;\r
- }\r
+ if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
+ d = SRAMRead(a);\r
+ elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
+ goto end;\r
}\r
#endif\r
\r
if (a<Pico.romsize) { d = *(u8 *)(Pico.rom+(a^1)); goto end; } // Rom\r
+ log_io(a, 8, 0);\r
if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram\r
\r
d=OtherRead16(a&~1, 8); if ((a&1)==0) d>>=8;\r
\r
- end:\r
-\r
- //if ((a&0xe0ffff)==0xe0AE57+0x69c)\r
- // dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
- //if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r
- // dprintf("r8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
-\r
- //if(a==0x200001) dprintf("r8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT());\r
- //dprintf("r8 : %06x, %02x @%06x [%03i]", a&0xffffff, (u8)d, SekPc, Pico.m.scanline);\r
+end:\r
#ifdef __debug_io\r
dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
#endif\r
#if defined(EMU_C68K) && defined(EMU_M68K)\r
- if(a>=Pico.romsize&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b) {\r
+ if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
lastread_a = a;\r
lastread_d[lrp_cyc++&15] = (u8)d;\r
}\r
#endif\r
- return (u8)d;\r
+ return d;\r
}\r
\r
-u16 CPU_CALL PicoRead16(u32 a)\r
+PICO_INTERNAL_ASM u32 PicoRead16(u32 a)\r
{\r
- u16 d=0;\r
+ u32 d=0;\r
\r
if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram\r
\r
\r
#if !(defined(EMU_C68K) && defined(EMU_M68K))\r
// sram\r
- if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) {\r
- d = (u16) SRAMRead(a);\r
+ if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
+ d = SRAMRead(a);\r
+ d |= d<<8;\r
+ elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
goto end;\r
}\r
#endif\r
\r
if (a<Pico.romsize) { d = *(u16 *)(Pico.rom+a); goto end; } // Rom\r
+ log_io(a, 16, 0);\r
\r
- d = (u16)OtherRead16(a, 16);\r
-\r
- end:\r
- //if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)\r
- // dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
+ d = OtherRead16(a, 16);\r
\r
+end:\r
#ifdef __debug_io\r
dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
#if defined(EMU_C68K) && defined(EMU_M68K)\r
- if(a>=Pico.romsize&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b) {\r
+ if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
lastread_a = a;\r
lastread_d[lrp_cyc++&15] = d;\r
}\r
return d;\r
}\r
\r
-u32 CPU_CALL PicoRead32(u32 a)\r
+PICO_INTERNAL_ASM u32 PicoRead32(u32 a)\r
{\r
u32 d=0;\r
\r
a&=0xfffffe;\r
\r
// sram\r
- if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) {\r
+ if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = (SRAMRead(a)<<16)|SRAMRead(a+2);\r
+ d |= d<<8;\r
+ elprintf(EL_SRAMIO, "sram r32 [%06x] %08x @ %06x", a, d, SekPc);\r
goto end;\r
}\r
\r
if (a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+a); d = (pm[0]<<16)|pm[1]; goto end; } // Rom\r
+ log_io(a, 32, 0);\r
\r
d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r
\r
- end:\r
+end:\r
#ifdef __debug_io\r
dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
#if defined(EMU_C68K) && defined(EMU_M68K)\r
- if(a>=Pico.romsize&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b) {\r
+ if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
lastread_a = a;\r
lastread_d[lrp_cyc++&15] = d;\r
}\r
// -----------------------------------------------------------------\r
// Write Ram\r
\r
-static void CPU_CALL PicoWrite8(u32 a,u8 d)\r
+#ifndef _ASM_MEMORY_C\r
+PICO_INTERNAL_ASM void PicoWrite8(u32 a,u8 d)\r
{\r
#ifdef __debug_io\r
dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
//if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r
+ //if(a==0x200000||a==0x200001) printf("w8 : %02x [%06x] @ %06x [%i]\n", d, a, SekPc, SekCyclesDoneT());\r
// dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
\r
-\r
- if ((a&0xe00000)==0xe00000) {\r
- if((a&0xffff)==0xf62a) dprintf("(f62a) = %02x [%i|%i] @ %x", d, Pico.m.scanline, SekCyclesDone(), SekPc);\r
- u8 *pm=(u8 *)(Pico.ram+((a^1)&0xffff)); pm[0]=d; return; } // Ram\r
+ if ((a&0xe00000)==0xe00000) { *(u8 *)(Pico.ram+((a^1)&0xffff))=d; return; } // Ram\r
+ log_io(a, 8, 1);\r
\r
a&=0xffffff;\r
- OtherWrite8(a,d,8);\r
+ OtherWrite8(a,d);\r
}\r
+#endif\r
\r
-static void CPU_CALL PicoWrite16(u32 a,u16 d)\r
+void PicoWrite16(u32 a,u16 d)\r
{\r
#ifdef __debug_io\r
dprintf("w16: %06x, %04x", a&0xffffff, d);\r
#if defined(EMU_C68K) && defined(EMU_M68K)\r
lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
- //if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)\r
- // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
\r
if ((a&0xe00000)==0xe00000) { *(u16 *)(Pico.ram+(a&0xfffe))=d; return; } // Ram\r
+ log_io(a, 16, 1);\r
\r
a&=0xfffffe;\r
OtherWrite16(a,d);\r
}\r
\r
-static void CPU_CALL PicoWrite32(u32 a,u32 d)\r
+static void PicoWrite32(u32 a,u32 d)\r
{\r
#ifdef __debug_io\r
dprintf("w32: %06x, %08x", a&0xffffff, d);\r
pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
return;\r
}\r
+ log_io(a, 32, 1);\r
\r
a&=0xfffffe;\r
OtherWrite16(a, (u16)(d>>16));\r
\r
\r
// -----------------------------------------------------------------\r
-void PicoMemSetup()\r
+PICO_INTERNAL void PicoMemSetup(void)\r
{\r
-#ifdef EMU_C68K\r
// Setup memory callbacks:\r
- PicoCpu.checkpc=PicoCheckPc;\r
- PicoCpu.fetch8 =PicoCpu.read8 =PicoRead8;\r
- PicoCpu.fetch16=PicoCpu.read16=PicoRead16;\r
- PicoCpu.fetch32=PicoCpu.read32=PicoRead32;\r
- PicoCpu.write8 =PicoWrite8;\r
- PicoCpu.write16=PicoWrite16;\r
- PicoCpu.write32=PicoWrite32;\r
+#ifdef EMU_C68K\r
+ PicoCpuCM68k.checkpc=PicoCheckPc;\r
+ PicoCpuCM68k.fetch8 =PicoCpuCM68k.read8 =PicoRead8;\r
+ PicoCpuCM68k.fetch16=PicoCpuCM68k.read16=PicoRead16;\r
+ PicoCpuCM68k.fetch32=PicoCpuCM68k.read32=PicoRead32;\r
+ PicoCpuCM68k.write8 =PicoWrite8;\r
+ PicoCpuCM68k.write16=PicoWrite16;\r
+ PicoCpuCM68k.write32=PicoWrite32;\r
+#endif\r
+#ifdef EMU_F68K\r
+ PicoCpuFM68k.read_byte =PicoRead8;\r
+ PicoCpuFM68k.read_word =PicoRead16;\r
+ PicoCpuFM68k.read_long =PicoRead32;\r
+ PicoCpuFM68k.write_byte=PicoWrite8;\r
+ PicoCpuFM68k.write_word=PicoWrite16;\r
+ PicoCpuFM68k.write_long=PicoWrite32;\r
+\r
+ // setup FAME fetchmap\r
+ {\r
+ int i;\r
+ // by default, point everything to fitst 64k of ROM\r
+ for (i = 0; i < M68K_FETCHBANK1; i++)\r
+ PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r
+ // now real ROM\r
+ for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)\r
+ PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom;\r
+ // .. and RAM\r
+ for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
+ PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r
+ }\r
#endif\r
}\r
\r
-#ifdef EMU_A68K\r
-struct A68KInter\r
-{\r
- u32 unknown;\r
- u8 (__fastcall *Read8) (u32 a);\r
- u16 (__fastcall *Read16)(u32 a);\r
- u32 (__fastcall *Read32)(u32 a);\r
- void (__fastcall *Write8) (u32 a,u8 d);\r
- void (__fastcall *Write16) (u32 a,u16 d);\r
- void (__fastcall *Write32) (u32 a,u32 d);\r
- void (__fastcall *ChangePc)(u32 a);\r
- u8 (__fastcall *PcRel8) (u32 a);\r
- u16 (__fastcall *PcRel16)(u32 a);\r
- u32 (__fastcall *PcRel32)(u32 a);\r
- u16 (__fastcall *Dir16)(u32 a);\r
- u32 (__fastcall *Dir32)(u32 a);\r
-};\r
-\r
-struct A68KInter a68k_memory_intf=\r
-{\r
- 0,\r
- PicoRead8,\r
- PicoRead16,\r
- PicoRead32,\r
- PicoWrite8,\r
- PicoWrite16,\r
- PicoWrite32,\r
- PicoCheckPc,\r
- PicoRead8,\r
- PicoRead16,\r
- PicoRead32,\r
- PicoRead16, // unused\r
- PicoRead32, // unused\r
-};\r
-#endif\r
\r
#ifdef EMU_M68K\r
unsigned int m68k_read_pcrelative_CD8 (unsigned int a);\r
unsigned int m68k_read_pcrelative_CD32(unsigned int a);\r
\r
// these are allowed to access RAM\r
-unsigned int m68k_read_pcrelative_8 (unsigned int a) {\r
+static unsigned int m68k_read_8 (unsigned int a, int do_fake) {\r
a&=0xffffff;\r
if(PicoMCD&1) return m68k_read_pcrelative_CD8(a);\r
if(a<Pico.romsize) return *(u8 *)(Pico.rom+(a^1)); // Rom\r
+#ifdef EMU_C68K\r
+ if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
+#endif\r
if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram\r
- return 0;//(u8) lastread_d;\r
+ return 0;\r
}\r
-unsigned int m68k_read_pcrelative_16(unsigned int a) {\r
+static unsigned int m68k_read_16(unsigned int a, int do_fake) {\r
a&=0xffffff;\r
if(PicoMCD&1) return m68k_read_pcrelative_CD16(a);\r
if(a<Pico.romsize) return *(u16 *)(Pico.rom+(a&~1)); // Rom\r
+#ifdef EMU_C68K\r
+ if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
+#endif\r
if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram\r
- return 0;//(u16) lastread_d;\r
+ return 0;\r
}\r
-unsigned int m68k_read_pcrelative_32(unsigned int a) {\r
+static unsigned int m68k_read_32(unsigned int a, int do_fake) {\r
a&=0xffffff;\r
if(PicoMCD&1) return m68k_read_pcrelative_CD32(a);\r
if(a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r
+#ifdef EMU_C68K\r
+ if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
+#endif\r
if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram\r
- return 0;//lastread_d;\r
+ return 0;\r
}\r
\r
-unsigned int m68k_read_immediate_16(unsigned int a) { return m68k_read_pcrelative_16(a); }\r
-unsigned int m68k_read_immediate_32(unsigned int a) { return m68k_read_pcrelative_32(a); }\r
-unsigned int m68k_read_disassembler_8 (unsigned int a) { return m68k_read_pcrelative_8 (a); }\r
-unsigned int m68k_read_disassembler_16(unsigned int a) { return m68k_read_pcrelative_16(a); }\r
-unsigned int m68k_read_disassembler_32(unsigned int a) { return m68k_read_pcrelative_32(a); }\r
+unsigned int m68k_read_pcrelative_8 (unsigned int a) { return m68k_read_8 (a, 1); }\r
+unsigned int m68k_read_pcrelative_16(unsigned int a) { return m68k_read_16(a, 1); }\r
+unsigned int m68k_read_pcrelative_32(unsigned int a) { return m68k_read_32(a, 1); }\r
+unsigned int m68k_read_immediate_16(unsigned int a) { return m68k_read_16(a, 0); }\r
+unsigned int m68k_read_immediate_32(unsigned int a) { return m68k_read_32(a, 0); }\r
+unsigned int m68k_read_disassembler_8 (unsigned int a) { return m68k_read_8 (a, 0); }\r
+unsigned int m68k_read_disassembler_16(unsigned int a) { return m68k_read_16(a, 0); }\r
+unsigned int m68k_read_disassembler_32(unsigned int a) { return m68k_read_32(a, 0); }\r
\r
#ifdef EMU_C68K\r
// ROM only\r
-unsigned int m68k_read_memory_8(unsigned int a) { if(a<Pico.romsize) return *(u8 *) (Pico.rom+(a^1)); return (u8) lastread_d[lrp_mus++&15]; }\r
-unsigned int m68k_read_memory_16(unsigned int a) { if(a<Pico.romsize) return *(u16 *)(Pico.rom+(a&~1));return (u16) lastread_d[lrp_mus++&15]; }\r
-unsigned int m68k_read_memory_32(unsigned int a) { if(a<Pico.romsize) {u16 *pm=(u16 *)(Pico.rom+(a&~1));return (pm[0]<<16)|pm[1];} return lastread_d[lrp_mus++&15]; }\r
+unsigned int m68k_read_memory_8(unsigned int a)\r
+{\r
+ u8 d;\r
+ if(a<Pico.romsize) d = *(u8 *) (Pico.rom+(a^1));\r
+ else d = (u8) lastread_d[lrp_mus++&15];\r
+#ifdef __debug_io\r
+ dprintf("r8_mu : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
+#endif\r
+ return d;\r
+}\r
+unsigned int m68k_read_memory_16(unsigned int a)\r
+{\r
+ u16 d;\r
+ if(a<Pico.romsize) d = *(u16 *)(Pico.rom+(a&~1));\r
+ else d = (u16) lastread_d[lrp_mus++&15];\r
+#ifdef __debug_io\r
+ dprintf("r16_mu: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
+#endif\r
+ return d;\r
+}\r
+unsigned int m68k_read_memory_32(unsigned int a)\r
+{\r
+ u32 d;\r
+ if(a<Pico.romsize) {u16 *pm=(u16 *)(Pico.rom+(a&~1));d=(pm[0]<<16)|pm[1];}\r
+ else d = lastread_d[lrp_mus++&15];\r
+#ifdef __debug_io\r
+ dprintf("r32_mu: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
+#endif\r
+ return d;\r
+}\r
\r
// ignore writes, Cyclone already done that\r
void m68k_write_memory_8(unsigned int address, unsigned int value) { lastwrite_mus_d[lwp_mus++&15] = value; }\r
void PicoWriteCD16w(unsigned int a, unsigned short d);\r
void PicoWriteCD32w(unsigned int a, unsigned int d);\r
\r
+/* it appears that Musashi doesn't always mask the unused bits */\r
unsigned int m68k_read_memory_8(unsigned int address)\r
{\r
- return (PicoMCD&1) ? PicoReadCD8w(address) : PicoRead8(address);\r
+ unsigned int d = (PicoMCD&1) ? PicoReadCD8w(address) : PicoRead8(address);\r
+ return d&0xff;\r
}\r
\r
unsigned int m68k_read_memory_16(unsigned int address)\r
{\r
- return (PicoMCD&1) ? PicoReadCD16w(address) : PicoRead16(address);\r
+ unsigned int d = (PicoMCD&1) ? PicoReadCD16w(address) : PicoRead16(address);\r
+ return d&0xffff;\r
}\r
\r
unsigned int m68k_read_memory_32(unsigned int address)\r
// -----------------------------------------------------------------\r
// z80 memhandlers\r
\r
-unsigned char z80_read(unsigned short a)\r
+PICO_INTERNAL unsigned char z80_read(unsigned short a)\r
{\r
u8 ret = 0;\r
\r
addr68k+=a&0x7fff;\r
\r
ret = (u8) PicoRead8(addr68k);\r
- //dprintf("z80->68k w8 : %06x, %02x", addr68k, ret);\r
+ elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);\r
goto end;\r
}\r
\r
// should not be needed || dprintf("z80_read RAM");\r
if (a<0x4000) { ret = (u8) Pico.zram[a&0x1fff]; goto end; }\r
\r
+ elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, ret);\r
+\r
end:\r
return ret;\r
}\r
\r
-unsigned short z80_read16(unsigned short a)\r
+PICO_INTERNAL unsigned short z80_read16(unsigned short a)\r
{\r
//dprintf("z80_read16");\r
\r
return (u16) ( (u16)z80_read(a) | ((u16)z80_read((u16)(a+1))<<8) );\r
}\r
\r
-void z80_write(unsigned char data, unsigned short a)\r
+PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a)\r
{\r
//if (a<0x4000)\r
// dprintf("z80 w8 : %06x, %02x @%04x", a, data, mz80GetRegisterValue(NULL, 0));\r
\r
if ((a>>13)==2) // 0x4000-0x5fff (Charles MacDonald)\r
{\r
- if(PicoOpt&1) emustatus|=YM2612Write(a, data);\r
+ if(PicoOpt&1) emustatus|=YM2612Write(a, data) & 1;\r
return;\r
}\r
\r
u32 addr68k;\r
addr68k=Pico.m.z80_bank68k<<15;\r
addr68k+=a&0x7fff;\r
+ elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);\r
PicoWrite8(addr68k, data);\r
- //dprintf("z80->68k w8 : %06x, %02x", addr68k, data);\r
return;\r
}\r
\r
// should not be needed, drZ80 knows how to access RAM itself || dprintf("z80_write RAM @ %08x", lr);\r
if (a<0x4000) { Pico.zram[a&0x1fff]=data; return; }\r
+\r
+ elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);\r
}\r
\r
-void z80_write16(unsigned short data, unsigned short a)\r
+PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a)\r
{\r
//dprintf("z80_write16");\r
\r
notaz.gp2x.de / picodrive.git / blobdiff