// For commercial use, separate licencing terms must be obtained.\r
\r
\r
-#define __debug_io\r
+//#define __debug_io\r
\r
#include "PicoInt.h"\r
\r
u32 PicoRead16(u32 a);\r
void PicoWrite8(u32 a,u8 d);\r
void PicoWriteRomHW_SSF2(u32 a,u32 d);\r
-void PicoWriteRomHW_in1 (u32 a,u32 d);\r
#endif\r
\r
\r
-#if defined(EMU_C68K) && defined(EMU_M68K)\r
-// cyclone debug mode\r
+#ifdef EMU_CORE_DEBUG\r
u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};\r
int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;\r
extern unsigned int ppop;\r
#endif\r
\r
\r
-static u32 CPU_CALL PicoCheckPc(u32 pc)\r
+static u32 PicoCheckPc(u32 pc)\r
{\r
u32 ret=0;\r
#if defined(EMU_C68K)\r
- pc-=PicoCpu.membase; // Get real pc\r
+ pc-=PicoCpuCM68k.membase; // Get real pc\r
// pc&=0xfffffe;\r
pc&=~1;\r
if ((pc<<8) == 0)\r
return (int)Pico.rom + Pico.romsize; // common crash condition, can happen if acc timing is off\r
}\r
\r
- PicoCpu.membase=PicoMemBase(pc&0x00ffffff);\r
- PicoCpu.membase-=pc&0xff000000;\r
+ PicoCpuCM68k.membase=PicoMemBase(pc&0x00ffffff);\r
+ PicoCpuCM68k.membase-=pc&0xff000000;\r
\r
- ret = PicoCpu.membase+pc;\r
+ ret = PicoCpuCM68k.membase+pc;\r
#endif\r
return ret;\r
}\r
// Read Rom and read Ram\r
\r
#ifndef _ASM_MEMORY_C\r
-PICO_INTERNAL_ASM u32 CPU_CALL PicoRead8(u32 a)\r
+PICO_INTERNAL_ASM u32 PicoRead8(u32 a)\r
{\r
u32 d=0;\r
\r
\r
a&=0xffffff;\r
\r
-#if !(defined(EMU_C68K) && defined(EMU_M68K))\r
+#ifndef EMU_CORE_DEBUG\r
// sram\r
- if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
+ if (a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = SRAMRead(a);\r
elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
goto end;\r
#ifdef __debug_io\r
dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
#endif\r
-#if defined(EMU_C68K) && defined(EMU_M68K)\r
- if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
+#ifdef EMU_CORE_DEBUG\r
+ if (a>=Pico.romsize) {\r
lastread_a = a;\r
lastread_d[lrp_cyc++&15] = (u8)d;\r
}\r
return d;\r
}\r
\r
-PICO_INTERNAL_ASM u32 CPU_CALL PicoRead16(u32 a)\r
+PICO_INTERNAL_ASM u32 PicoRead16(u32 a)\r
{\r
u32 d=0;\r
\r
\r
a&=0xfffffe;\r
\r
-#if !(defined(EMU_C68K) && defined(EMU_M68K))\r
+#ifndef EMU_CORE_DEBUG\r
// sram\r
- if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
+ if (a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = SRAMRead(a);\r
d |= d<<8;\r
elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);\r
#ifdef __debug_io\r
dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
-#if defined(EMU_C68K) && defined(EMU_M68K)\r
- if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
+#ifdef EMU_CORE_DEBUG\r
+ if (a>=Pico.romsize) {\r
lastread_a = a;\r
lastread_d[lrp_cyc++&15] = d;\r
}\r
return d;\r
}\r
\r
-PICO_INTERNAL_ASM u32 CPU_CALL PicoRead32(u32 a)\r
+PICO_INTERNAL_ASM u32 PicoRead32(u32 a)\r
{\r
u32 d=0;\r
\r
#ifdef __debug_io\r
dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
-#if defined(EMU_C68K) && defined(EMU_M68K)\r
- if(a>=Pico.romsize/*&&(ppop&0x3f)!=0x3a&&(ppop&0x3f)!=0x3b*/) {\r
+#ifdef EMU_CORE_DEBUG\r
+ if (a>=Pico.romsize) {\r
lastread_a = a;\r
lastread_d[lrp_cyc++&15] = d;\r
}\r
// -----------------------------------------------------------------\r
// Write Ram\r
\r
-#ifndef _ASM_MEMORY_C\r
-PICO_INTERNAL_ASM void CPU_CALL PicoWrite8(u32 a,u8 d)\r
+#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)\r
+PICO_INTERNAL_ASM void PicoWrite8(u32 a,u8 d)\r
{\r
#ifdef __debug_io\r
dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
-#if defined(EMU_C68K) && defined(EMU_M68K)\r
+#ifdef EMU_CORE_DEBUG\r
lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
- //if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r
- //if(a==0x200000||a==0x200001) printf("w8 : %02x [%06x] @ %06x [%i]\n", d, a, SekPc, SekCyclesDoneT());\r
- // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
\r
if ((a&0xe00000)==0xe00000) { *(u8 *)(Pico.ram+((a^1)&0xffff))=d; return; } // Ram\r
log_io(a, 8, 1);\r
}\r
#endif\r
\r
-void CPU_CALL PicoWrite16(u32 a,u16 d)\r
+void PicoWrite16(u32 a,u16 d)\r
{\r
#ifdef __debug_io\r
dprintf("w16: %06x, %04x", a&0xffffff, d);\r
#endif\r
-#if defined(EMU_C68K) && defined(EMU_M68K)\r
+#ifdef EMU_CORE_DEBUG\r
lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
\r
OtherWrite16(a,d);\r
}\r
\r
-static void CPU_CALL PicoWrite32(u32 a,u32 d)\r
+static void PicoWrite32(u32 a,u32 d)\r
{\r
#ifdef __debug_io\r
dprintf("w32: %06x, %08x", a&0xffffff, d);\r
#endif\r
-#if defined(EMU_C68K) && defined(EMU_M68K)\r
+#ifdef EMU_CORE_DEBUG\r
lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
\r
{\r
// Setup memory callbacks:\r
#ifdef EMU_C68K\r
- PicoCpu.checkpc=PicoCheckPc;\r
- PicoCpu.fetch8 =PicoCpu.read8 =PicoRead8;\r
- PicoCpu.fetch16=PicoCpu.read16=PicoRead16;\r
- PicoCpu.fetch32=PicoCpu.read32=PicoRead32;\r
- PicoCpu.write8 =PicoWrite8;\r
- PicoCpu.write16=PicoWrite16;\r
- PicoCpu.write32=PicoWrite32;\r
+ PicoCpuCM68k.checkpc=PicoCheckPc;\r
+ PicoCpuCM68k.fetch8 =PicoCpuCM68k.read8 =PicoRead8;\r
+ PicoCpuCM68k.fetch16=PicoCpuCM68k.read16=PicoRead16;\r
+ PicoCpuCM68k.fetch32=PicoCpuCM68k.read32=PicoRead32;\r
+ PicoCpuCM68k.write8 =PicoWrite8;\r
+ PicoCpuCM68k.write16=PicoWrite16;\r
+ PicoCpuCM68k.write32=PicoWrite32;\r
#endif\r
#ifdef EMU_F68K\r
- PicoCpuM68k.read_byte =PicoRead8;\r
- PicoCpuM68k.read_word =PicoRead16;\r
- PicoCpuM68k.read_long =PicoRead32;\r
- PicoCpuM68k.write_byte=PicoWrite8;\r
- PicoCpuM68k.write_word=PicoWrite16;\r
- PicoCpuM68k.write_long=PicoWrite32;\r
+ PicoCpuFM68k.read_byte =PicoRead8;\r
+ PicoCpuFM68k.read_word =PicoRead16;\r
+ PicoCpuFM68k.read_long =PicoRead32;\r
+ PicoCpuFM68k.write_byte=PicoWrite8;\r
+ PicoCpuFM68k.write_word=PicoWrite16;\r
+ PicoCpuFM68k.write_long=PicoWrite32;\r
+\r
+ // setup FAME fetchmap\r
+ {\r
+ int i;\r
+ // by default, point everything to fitst 64k of ROM\r
+ for (i = 0; i < M68K_FETCHBANK1; i++)\r
+ PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS));\r
+ // now real ROM\r
+ for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)\r
+ PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom;\r
+ // .. and RAM\r
+ for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
+ PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r
+ }\r
#endif\r
}\r
\r
unsigned int m68k_read_pcrelative_CD32(unsigned int a);\r
\r
// these are allowed to access RAM\r
-static unsigned int m68k_read_8 (unsigned int a, int do_fake) {\r
+static unsigned int m68k_read_8 (unsigned int a, int do_fake)\r
+{\r
a&=0xffffff;\r
- if(PicoMCD&1) return m68k_read_pcrelative_CD8(a);\r
- if(a<Pico.romsize) return *(u8 *)(Pico.rom+(a^1)); // Rom\r
-#ifdef EMU_C68K\r
+ if(a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k) return *(u8 *)(Pico.rom+(a^1)); // Rom\r
+#ifdef EMU_CORE_DEBUG\r
if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
#endif\r
+ if(PicoMCD&1) return m68k_read_pcrelative_CD8(a);\r
if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram\r
return 0;\r
}\r
-static unsigned int m68k_read_16(unsigned int a, int do_fake) {\r
+static unsigned int m68k_read_16(unsigned int a, int do_fake)\r
+{\r
a&=0xffffff;\r
- if(PicoMCD&1) return m68k_read_pcrelative_CD16(a);\r
- if(a<Pico.romsize) return *(u16 *)(Pico.rom+(a&~1)); // Rom\r
-#ifdef EMU_C68K\r
+ if(a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k) return *(u16 *)(Pico.rom+(a&~1)); // Rom\r
+#ifdef EMU_CORE_DEBUG\r
if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
#endif\r
+ if(PicoMCD&1) return m68k_read_pcrelative_CD16(a);\r
if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram\r
return 0;\r
}\r
-static unsigned int m68k_read_32(unsigned int a, int do_fake) {\r
+static unsigned int m68k_read_32(unsigned int a, int do_fake)\r
+{\r
a&=0xffffff;\r
- if(PicoMCD&1) return m68k_read_pcrelative_CD32(a);\r
- if(a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r
-#ifdef EMU_C68K\r
+ if(a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r
+#ifdef EMU_CORE_DEBUG\r
if(do_fake&&((ppop&0x3f)==0x3a||(ppop&0x3f)==0x3b)) return lastread_d[lrp_mus++&15];\r
#endif\r
+ if(PicoMCD&1) return m68k_read_pcrelative_CD32(a);\r
if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram\r
return 0;\r
}\r
unsigned int m68k_read_disassembler_16(unsigned int a) { return m68k_read_16(a, 0); }\r
unsigned int m68k_read_disassembler_32(unsigned int a) { return m68k_read_32(a, 0); }\r
\r
-#ifdef EMU_C68K\r
+#ifdef EMU_CORE_DEBUG\r
// ROM only\r
unsigned int m68k_read_memory_8(unsigned int a)\r
{\r
u8 d;\r
- if(a<Pico.romsize) d = *(u8 *) (Pico.rom+(a^1));\r
+ if (a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k)\r
+ d = *(u8 *) (Pico.rom+(a^1));\r
else d = (u8) lastread_d[lrp_mus++&15];\r
#ifdef __debug_io\r
dprintf("r8_mu : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
unsigned int m68k_read_memory_16(unsigned int a)\r
{\r
u16 d;\r
- if(a<Pico.romsize) d = *(u16 *)(Pico.rom+(a&~1));\r
+ if (a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k)\r
+ d = *(u16 *)(Pico.rom+(a&~1));\r
else d = (u16) lastread_d[lrp_mus++&15];\r
#ifdef __debug_io\r
dprintf("r16_mu: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
unsigned int m68k_read_memory_32(unsigned int a)\r
{\r
u32 d;\r
- if(a<Pico.romsize) {u16 *pm=(u16 *)(Pico.rom+(a&~1));d=(pm[0]<<16)|pm[1];}\r
+ if (a<Pico.romsize && m68ki_cpu_p==&PicoCpuMM68k)\r
+ { u16 *pm=(u16 *)(Pico.rom+(a&~1));d=(pm[0]<<16)|pm[1]; }\r
+ else if (a <= 0x78) d = m68k_read_32(a, 0);\r
else d = lastread_d[lrp_mus++&15];\r
#ifdef __debug_io\r
dprintf("r32_mu: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
{\r
u8 ret = 0;\r
\r
+#ifndef _USE_DRZ80\r
+ if (a<0x4000) return Pico.zram[a&0x1fff];\r
+#endif\r
+\r
if ((a>>13)==2) // 0x4000-0x5fff (Charles MacDonald)\r
{\r
- if(PicoOpt&1) ret = (u8) YM2612Read();\r
- goto end;\r
+ if (PicoOpt&1) ret = (u8) YM2612Read();\r
+ return ret;\r
}\r
\r
if (a>=0x8000)\r
\r
ret = (u8) PicoRead8(addr68k);\r
elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);\r
- goto end;\r
+ return ret;\r
}\r
\r
+#ifdef _USE_DRZ80\r
// should not be needed || dprintf("z80_read RAM");\r
- if (a<0x4000) { ret = (u8) Pico.zram[a&0x1fff]; goto end; }\r
+ if (a<0x4000) return Pico.zram[a&0x1fff];\r
+#endif\r
\r
elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, ret);\r
-\r
-end:\r
return ret;\r
}\r
\r
-PICO_INTERNAL unsigned short z80_read16(unsigned short a)\r
-{\r
- //dprintf("z80_read16");\r
-\r
- return (u16) ( (u16)z80_read(a) | ((u16)z80_read((u16)(a+1))<<8) );\r
-}\r
-\r
+#ifndef _USE_CZ80\r
PICO_INTERNAL_ASM void z80_write(unsigned char data, unsigned short a)\r
+#else\r
+PICO_INTERNAL_ASM void z80_write(unsigned int a, unsigned char data)\r
+#endif\r
{\r
- //if (a<0x4000)\r
- // dprintf("z80 w8 : %06x, %02x @%04x", a, data, mz80GetRegisterValue(NULL, 0));\r
+#ifndef _USE_DRZ80\r
+ if (a<0x4000) { Pico.zram[a&0x1fff]=data; return; }\r
+#endif\r
\r
if ((a>>13)==2) // 0x4000-0x5fff (Charles MacDonald)\r
{\r
return;\r
}\r
\r
+#ifdef _USE_DRZ80\r
// should not be needed, drZ80 knows how to access RAM itself || dprintf("z80_write RAM @ %08x", lr);\r
if (a<0x4000) { Pico.zram[a&0x1fff]=data; return; }\r
+#endif\r
\r
elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);\r
}\r
\r
-PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a)\r
+#ifndef _USE_CZ80\r
+PICO_INTERNAL unsigned short z80_read16(unsigned short a)\r
{\r
- //dprintf("z80_write16");\r
+ return (u16) ( (u16)z80_read(a) | ((u16)z80_read((u16)(a+1))<<8) );\r
+}\r
\r
+PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a)\r
+{\r
z80_write((unsigned char) data,a);\r
z80_write((unsigned char)(data>>8),(u16)(a+1));\r
}\r
+#endif\r
\r
notaz.gp2x.de / picodrive.git / blobdiff