#ifdef _ASM_MEMORY_C\r
u32 PicoRead8(u32 a);\r
u32 PicoRead16(u32 a);\r
+void PicoWrite8(u32 a,u8 d);\r
void PicoWriteRomHW_SSF2(u32 a,u32 d);\r
void PicoWriteRomHW_in1 (u32 a,u32 d);\r
#endif\r
extern unsigned int ppop;\r
#endif\r
\r
+#ifdef IO_STATS\r
+void log_io(unsigned int addr, int bits, int rw);\r
+#else\r
+#define log_io(...)\r
+#endif\r
+\r
#if defined(EMU_C68K) || defined(EMU_A68K)\r
static __inline int PicoMemBase(u32 pc)\r
{\r
// pc&=0xfffffe;\r
pc&=~1;\r
if ((pc<<8) == 0)\r
+ {\r
+ printf("%i:%03i: game crash detected @ %06x\n", Pico.m.frame_count, Pico.m.scanline, SekPc);\r
return (int)Pico.rom + Pico.romsize; // common crash condition, can happen if acc timing is off\r
+ }\r
\r
PicoCpu.membase=PicoMemBase(pc&0x00ffffff);\r
PicoCpu.membase-=pc&0xff000000;\r
\r
// -----------------------------------------------------------------\r
\r
-#ifndef _ASM_MEMORY_C\r
-// address must already be checked\r
-static int SRAMRead(u32 a)\r
+int PadRead(int i)\r
{\r
- u8 *d = SRam.data-SRam.start+a;\r
- return (d[0]<<8)|d[1];\r
+ int pad,value,data_reg;\r
+ pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU\r
+ data_reg=Pico.ioports[i+1];\r
+\r
+ // orr the bits, which are set as output\r
+ value = data_reg&(Pico.ioports[i+4]|0x80);\r
+\r
+ if(PicoOpt & 0x20) { // 6 button gamepad enabled\r
+ int phase = Pico.m.padTHPhase[i];\r
+\r
+ if(phase == 2 && !(data_reg&0x40)) { // TH\r
+ value|=(pad&0xc0)>>2; // ?0SA 0000\r
+ return value;\r
+ } else if(phase == 3) {\r
+ if(data_reg&0x40)\r
+ value|=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ\r
+ else\r
+ value|=((pad&0xc0)>>2)|0x0f; // ?0SA 1111\r
+ return value;\r
+ }\r
+ }\r
+\r
+ if(data_reg&0x40) // TH\r
+ value|=(pad&0x3f); // ?1CB RLDU\r
+ else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU\r
+\r
+ return value; // will mirror later\r
}\r
+\r
+\r
+#ifndef _ASM_MEMORY_C\r
+static\r
#endif\r
+u32 SRAMRead(u32 a)\r
+{\r
+ unsigned int sreg = Pico.m.sram_reg;\r
+ if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM\r
+ Pico.m.sram_reg|=0x10; // should be normal SRAM\r
+ }\r
+ if(sreg & 4) // EEPROM read\r
+ return SRAMReadEEPROM();\r
+ else // if(sreg & 1) // (sreg&5) is one of prerequisites\r
+ return *(u8 *)(SRam.data-SRam.start+a);\r
+}\r
\r
+static void SRAMWrite(u32 a, u32 d)\r
+{\r
+ dprintf("sram_w: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
+ unsigned int sreg = Pico.m.sram_reg;\r
+ if(!(sreg & 0x10)) {\r
+ // not detected SRAM\r
+ if((a&~1)==0x200000) {\r
+ Pico.m.sram_reg|=4; // this should be a game with EEPROM (like NBA Jam)\r
+ SRam.start=0x200000; SRam.end=SRam.start+1;\r
+ }\r
+ Pico.m.sram_reg|=0x10;\r
+ }\r
+ if(sreg & 4) { // EEPROM write\r
+ if(SekCyclesDoneT()-lastSSRamWrite < 46) {\r
+ // just update pending state\r
+ SRAMUpdPending(a, d);\r
+ } else {\r
+ SRAMWriteEEPROM(sreg>>6); // execute pending\r
+ SRAMUpdPending(a, d);\r
+ lastSSRamWrite = SekCyclesDoneT();\r
+ }\r
+ } else if(!(sreg & 2)) {\r
+ u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
+ if(*pm != (u8)d) {\r
+ SRam.changed = 1;\r
+ *pm=(u8)d;\r
+ }\r
+ }\r
+}\r
\r
// for nonstandard reads\r
#ifndef _ASM_MEMORY_C\r
//if(a==0x200000) dprintf("cc : %02x @ %06x [%i|%i]", d, SekPc, SekCyclesDoneT(), SekCyclesDone());\r
//if(a==0x200001) dprintf("w8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT());\r
if(a >= SRam.start && a <= SRam.end) {\r
- dprintf("sram w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
- unsigned int sreg = Pico.m.sram_reg;\r
- if(!(sreg & 0x10)) {\r
- // not detected SRAM\r
- if((a&~1)==0x200000) {\r
- Pico.m.sram_reg|=4; // this should be a game with EEPROM (like NBA Jam)\r
- SRam.start=0x200000; SRam.end=SRam.start+1;\r
- }\r
- Pico.m.sram_reg|=0x10;\r
- }\r
- if(sreg & 4) { // EEPROM write\r
- if(SekCyclesDoneT()-lastSSRamWrite < 46) {\r
- // just update pending state\r
- SRAMUpdPending(a, d);\r
- } else {\r
- SRAMWriteEEPROM(sreg>>6); // execute pending\r
- SRAMUpdPending(a, d);\r
- lastSSRamWrite = SekCyclesDoneT();\r
- }\r
- } else if(!(sreg & 2)) {\r
- u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
- if(*pm != (u8)d) {\r
- SRam.changed = 1;\r
- *pm=(u8)d;\r
- }\r
- }\r
+ SRAMWrite(a, d);\r
return;\r
}\r
\r
\r
#if !(defined(EMU_C68K) && defined(EMU_M68K))\r
// sram\r
- if(a >= SRam.start && a <= SRam.end) {\r
- unsigned int sreg = Pico.m.sram_reg;\r
- if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM\r
- Pico.m.sram_reg|=0x10; // should be normal SRAM\r
- }\r
- if(sreg & 4) { // EEPROM read\r
- d = SRAMReadEEPROM();\r
- goto end;\r
- } else if(sreg & 1) {\r
- d = *(u8 *)(SRam.data-SRam.start+a);\r
- goto end;\r
- }\r
+ if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
+ d = SRAMRead(a);\r
+ goto end;\r
}\r
#endif\r
\r
if (a<Pico.romsize) { d = *(u8 *)(Pico.rom+(a^1)); goto end; } // Rom\r
+ log_io(a, 8, 0);\r
if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram\r
\r
d=OtherRead16(a&~1, 8); if ((a&1)==0) d>>=8;\r
//if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r
// dprintf("r8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
\r
- //if(a==0x200001) dprintf("r8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT());\r
+ //if(a==0x200001||a==0x200000) printf("r8 : %02x [%06x] @ %06x [%i]\n", d, a, SekPc, SekCyclesDoneT());\r
//dprintf("r8 : %06x, %02x @%06x [%03i]", a&0xffffff, (u8)d, SekPc, Pico.m.scanline);\r
#ifdef __debug_io\r
dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
\r
#if !(defined(EMU_C68K) && defined(EMU_M68K))\r
// sram\r
- if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) {\r
+ if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = SRAMRead(a);\r
+ d |= d<<8;\r
goto end;\r
}\r
#endif\r
\r
if (a<Pico.romsize) { d = *(u16 *)(Pico.rom+a); goto end; } // Rom\r
+ log_io(a, 16, 0);\r
\r
d = OtherRead16(a, 16);\r
\r
end:\r
//if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)\r
// dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
+ //if(a==0x200000) printf("r16: %04x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
\r
#ifdef __debug_io\r
dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
a&=0xfffffe;\r
\r
// sram\r
- if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) {\r
+ if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = (SRAMRead(a)<<16)|SRAMRead(a+2);\r
+ d |= d<<8;\r
goto end;\r
}\r
\r
if (a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+a); d = (pm[0]<<16)|pm[1]; goto end; } // Rom\r
+ log_io(a, 32, 0);\r
\r
d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r
\r
end:\r
+ //if(a==0x200000) printf("r32: %08x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
#ifdef __debug_io\r
dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
// -----------------------------------------------------------------\r
// Write Ram\r
\r
-static void CPU_CALL PicoWrite8(u32 a,u8 d)\r
+#ifndef _ASM_MEMORY_C\r
+PICO_INTERNAL_ASM void CPU_CALL PicoWrite8(u32 a,u8 d)\r
{\r
#ifdef __debug_io\r
dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
//if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r
+ //if(a==0x200000||a==0x200001) printf("w8 : %02x [%06x] @ %06x [%i]\n", d, a, SekPc, SekCyclesDoneT());\r
// dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
\r
if ((a&0xe00000)==0xe00000) { *(u8 *)(Pico.ram+((a^1)&0xffff))=d; return; } // Ram\r
+ log_io(a, 8, 1);\r
\r
a&=0xffffff;\r
- OtherWrite8(a,d,8);\r
+ OtherWrite8(a,d);\r
}\r
+#endif\r
\r
void CPU_CALL PicoWrite16(u32 a,u16 d)\r
{\r
#endif\r
//if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)\r
// dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
+ //if(a==0x200000) printf("w16: %04x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
\r
if ((a&0xe00000)==0xe00000) { *(u16 *)(Pico.ram+(a&0xfffe))=d; return; } // Ram\r
+ log_io(a, 16, 1);\r
\r
a&=0xfffffe;\r
OtherWrite16(a,d);\r
#if defined(EMU_C68K) && defined(EMU_M68K)\r
lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
+ //if(a==0x200000) printf("w32: %08x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
\r
if ((a&0xe00000)==0xe00000)\r
{\r
pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r
return;\r
}\r
+ log_io(a, 32, 1);\r
\r
a&=0xfffffe;\r
OtherWrite16(a, (u16)(d>>16));\r
addr68k+=a&0x7fff;\r
\r
ret = (u8) PicoRead8(addr68k);\r
- //dprintf("z80->68k w8 : %06x, %02x", addr68k, ret);\r
+ elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);\r
goto end;\r
}\r
\r
// should not be needed || dprintf("z80_read RAM");\r
if (a<0x4000) { ret = (u8) Pico.zram[a&0x1fff]; goto end; }\r
\r
+ elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, ret);\r
+\r
end:\r
return ret;\r
}\r
u32 addr68k;\r
addr68k=Pico.m.z80_bank68k<<15;\r
addr68k+=a&0x7fff;\r
+ elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);\r
PicoWrite8(addr68k, data);\r
- //dprintf("z80->68k w8 : %06x, %02x", addr68k, data);\r
return;\r
}\r
\r
// should not be needed, drZ80 knows how to access RAM itself || dprintf("z80_write RAM @ %08x", lr);\r
if (a<0x4000) { Pico.zram[a&0x1fff]=data; return; }\r
+\r
+ elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);\r
}\r
\r
PICO_INTERNAL void z80_write16(unsigned short data, unsigned short a)\r
notaz.gp2x.de / picodrive.git / blobdiff