void z80WriteBusReq(u32 d)
{
d&=1; d^=1;
- if (Pico.m.scanline != -1)
{
- if(!d) {
+ if (!d)
+ {
// this is for a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)
if (Pico.m.z80Run) {
int lineCycles;
z80stopCycle = SekCyclesDone();
- if (Pico.m.z80Run&2)
+ if ((Pico.m.z80Run&2) && Pico.m.scanline != -1)
lineCycles=(488-SekCyclesLeft)&0x1ff;
else lineCycles=z80stopCycle-z80startCycle; // z80 was started at current line
- if (lineCycles > 0 && lineCycles <= 488) {
+ if (lineCycles > 0) { // && lineCycles <= 488) {
//dprintf("zrun: %i/%i cycles", lineCycles, (lineCycles>>1)-(lineCycles>>5));
lineCycles=(lineCycles>>1)-(lineCycles>>5);
- z80_run(lineCycles);
+ z80_run_nr(lineCycles);
}
}
} else {
goto end;
}
-#ifndef _ASM_MEMORY_C
- if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }
-#endif
-
d = OtherRead16End(a, realsize);
end:
#endif
void OtherWrite8(u32 a,u32 d)
{
-#ifndef _ASM_MEMORY_C
+#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)
if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram
if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d)&1; return; } // FM Sound
if(!(d&1)) z80_reset();
return;
}
-#ifndef _ASM_MEMORY_C
+#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)
if ((a&0xff7f00)==0xa06000) // Z80 BANK register
{
Pico.m.z80_bank68k>>=1;
#endif
void OtherWrite16(u32 a,u32 d)
{
- if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }
if (a==0xa11100) { z80WriteBusReq(d>>8); return; }
if (a==0xa11200) { dprintf("write z80reset: %04x", d); if(!(d&0x100)) z80_reset(); return; }
if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports
#ifndef _CD_MEMORY_C
if (a >= SRam.start && a <= SRam.end) {
elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d, SekPc);
- if ((a&0x16)==0x10) { // detected, not EEPROM, write not disabled
+ if ((Pico.m.sram_reg&0x16)==0x10) { // detected, not EEPROM, write not disabled
u8 *pm=(u8 *)(SRam.data-SRam.start+a);
*pm++=d>>8;
*pm++=d;