0x0a,0x0b,0x0b,0x0b,0x0c,0x0c,0x0c,0x0d,\r
};\r
\r
-// vcounter values for PicoFrameSimple \r
+// vcounter values for PicoFrameSimple\r
const unsigned short vcounts[] = {\r
0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,\r
8, 8, 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16,\r
\r
// sram_reg: LAtd sela (L=pending SCL, A=pending SDA, t=type(1==uses 0x200000 for SCL and 2K bytes),\r
// d=SRAM was detected (header or by access), s=started, e=save is EEPROM, l=old SCL, a=old SDA)\r
-void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)\r
+PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)\r
{\r
unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.sram_addr, scyc = Pico.m.sram_cycle, ssa = Pico.m.sram_slave;\r
\r
- //dprintf("[%02x]", d);\r
+ //printf("EEPROM write %i\n", d&3);\r
sreg |= saddr&0xc000; // we store word count in add reg: dw?a aaaa ... (d=word count detected, w=words(0==use 2 words, else 1))\r
saddr&=0x1fff;\r
\r
if((sreg & 1) && !(d&1)) {\r
// ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter\r
//dprintf("-start-");\r
- if(!(sreg&0x8000) && scyc >= 9) {\r
- if(scyc != 28) sreg |= 0x4000; // 1 word\r
+ if(!(sreg&0x8000) && scyc >= 9) {\r
+ if(scyc != 28) sreg |= 0x4000; // 1 word\r
//dprintf("detected word count: %i", scyc==28 ? 2 : 1);\r
- sreg |= 0x8000;\r
- }\r
+ sreg |= 0x8000;\r
+ }\r
//saddr = 0;\r
scyc = 0;\r
sreg |= 8;\r
else if((sreg & 8) && !(sreg & 2) && (d&2)) {\r
// we are started and SCL went high - next cycle\r
scyc++; // pre-increment\r
- if(sreg & 0x20) {\r
+ if(sreg & 0x20) {\r
// X24C02+\r
- if((ssa&1) && scyc == 18) {\r
- scyc = 9;\r
- saddr++; // next address in read mode\r
- if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
- }\r
- else if((sreg&0x4000) && scyc == 27) scyc = 18;\r
- else if(scyc == 36) scyc = 27;\r
- } else {\r
- // X24C01\r
+ if((ssa&1) && scyc == 18) {\r
+ scyc = 9;\r
+ saddr++; // next address in read mode\r
+ if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
+ }\r
+ else if((sreg&0x4000) && scyc == 27) scyc = 18;\r
+ else if(scyc == 36) scyc = 27;\r
+ } else {\r
+ // X24C01\r
if(scyc == 18) {\r
scyc = 9; // wrap\r
if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode\r
- }\r
- }\r
- //dprintf("scyc: %i", scyc);\r
+ }\r
+ }\r
+ //dprintf("scyc: %i", scyc);\r
}\r
else if((sreg & 8) && (sreg & 2) && !(d&2)) {\r
// we are started and SCL went low (falling edge)\r
if(sreg & 0x20) {\r
- // X24C02+\r
- if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles\r
- else if( (!(sreg&0x4000) && scyc > 27) || ((sreg&0x4000) && scyc > 18) ) {\r
+ // X24C02+\r
+ if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles\r
+ else if( (!(sreg&0x4000) && scyc > 27) || ((sreg&0x4000) && scyc > 18) ) {\r
if(!(ssa&1)) {\r
// data write\r
unsigned char *pm=SRam.data+saddr;\r
} else if(scyc > 9) {\r
if(!(ssa&1)) {\r
// we latch another addr bit\r
- saddr<<=1;\r
- if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
- saddr|=d&1;\r
+ saddr<<=1;\r
+ if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
+ saddr|=d&1;\r
//if(scyc==17||scyc==26) dprintf("addr reg done: %x", saddr);\r
- }\r
+ }\r
} else {\r
- // slave address\r
- ssa<<=1; ssa|=d&1;\r
+ // slave address\r
+ ssa<<=1; ssa|=d&1;\r
//if(scyc==8) dprintf("slave done: %x", ssa);\r
}\r
- } else {\r
- // X24C01\r
+ } else {\r
+ // X24C01\r
if(scyc == 9); // ACK cycle, do nothing\r
else if(scyc > 9) {\r
if(!(saddr&1)) {\r
saddr<<=1; saddr|=d&1; saddr&=0xff;\r
//if(scyc==8) dprintf("addr done: %x", saddr>>1);\r
}\r
- }\r
+ }\r
}\r
\r
sreg &= ~3; sreg |= d&3; // remember SCL and SDA\r
Pico.m.sram_slave= (unsigned char) ssa;\r
}\r
\r
-unsigned int SRAMReadEEPROM()\r
+PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void)\r
{\r
unsigned int shift, d=0;\r
unsigned int sreg, saddr, scyc, ssa;\r
// started and first command word received\r
shift = 17-scyc;\r
if(sreg & 0x20) {\r
- // X24C02+\r
+ // X24C02+\r
if(ssa&1) {\r
//dprintf("read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);\r
- d = (SRam.data[saddr]>>shift)&1;\r
- }\r
- } else {\r
- // X24C01\r
+ d = (SRam.data[saddr]>>shift)&1;\r
+ }\r
+ } else {\r
+ // X24C01\r
if(saddr&1) {\r
- d = (SRam.data[saddr>>1]>>shift)&1;\r
- }\r
- }\r
+ d = (SRam.data[saddr>>1]>>shift)&1;\r
+ }\r
+ }\r
}\r
//else dprintf("r ack");\r
\r
return d;\r
}\r
\r
-void SRAMUpdPending(unsigned int a, unsigned int d)\r
+PICO_INTERNAL void SRAMUpdPending(unsigned int a, unsigned int d)\r
{\r
unsigned int sreg = Pico.m.sram_reg;\r
\r
\r
Pico.m.sram_reg = (unsigned char) sreg;\r
}\r
+\r
+\r
+#ifndef _ASM_MISC_C\r
+PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count)\r
+{\r
+ while (count--)\r
+ *dest++ = *src++;\r
+}\r
+\r
+\r
+PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count)\r
+{\r
+ unsigned char *src_ = src;\r
+\r
+ for (; count; count--, src_ += 2)\r
+ *dest++ = (src_[0] << 8) | src_[1];\r
+}\r
+\r
+\r
+PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count)\r
+{\r
+ while (count--)\r
+ *dest++ = *src++;\r
+}\r
+\r
+\r
+PICO_INTERNAL_ASM void memset32(int *dest, int c, int count)\r
+{\r
+ while (count--)\r
+ *dest++ = c;\r
+}\r
+#endif\r
+\r
notaz.gp2x.de / picodrive.git / blobdiff