sram handling refactored

[picodrive.git] / Pico / Misc.c

diff --git a/Pico/Misc.c b/Pico/Misc.c
index 2a0e569..8e89a4f 100644 (file)
--- a/Pico/Misc.c
+++ b/Pico/Misc.c
@@ -145,7 +145,7 @@ PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)
 {\r
   unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.sram_addr, scyc = Pico.m.sram_cycle, ssa = Pico.m.sram_slave;\r
 \r
-  //dprintf("[%02x]", d);\r
+  //printf("EEPROM write %i\n", d&3);\r
   sreg |= saddr&0xc000; // we store word count in add reg: dw?a aaaa ...  (d=word count detected, w=words(0==use 2 words, else 1))\r
   saddr&=0x1fff;\r
 \r
@@ -154,11 +154,11 @@ PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)
     if((sreg & 1) && !(d&1)) {\r
       // ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter\r
       //dprintf("-start-");\r
-         if(!(sreg&0x8000) && scyc >= 9) {\r
-           if(scyc != 28) sreg |= 0x4000; // 1 word\r
+      if(!(sreg&0x8000) && scyc >= 9) {\r
+        if(scyc != 28) sreg |= 0x4000; // 1 word\r
         //dprintf("detected word count: %i", scyc==28 ? 2 : 1);\r
-               sreg |= 0x8000;\r
-         }\r
+        sreg |= 0x8000;\r
+      }\r
       //saddr = 0;\r
       scyc = 0;\r
       sreg |= 8;\r
@@ -171,30 +171,30 @@ PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)
   else if((sreg & 8) && !(sreg & 2) && (d&2)) {\r
     // we are started and SCL went high - next cycle\r
     scyc++; // pre-increment\r
-       if(sreg & 0x20) {\r
+    if(sreg & 0x20) {\r
       // X24C02+\r
-         if((ssa&1) && scyc == 18) {\r
-           scyc = 9;\r
-               saddr++; // next address in read mode\r
-               if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
-         }\r
-         else if((sreg&0x4000) && scyc == 27) scyc = 18;\r
-         else if(scyc == 36) scyc = 27;\r
-       } else {\r
-         // X24C01\r
+      if((ssa&1) && scyc == 18) {\r
+        scyc = 9;\r
+        saddr++; // next address in read mode\r
+        if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
+      }\r
+      else if((sreg&0x4000) && scyc == 27) scyc = 18;\r
+      else if(scyc == 36) scyc = 27;\r
+    } else {\r
+      // X24C01\r
       if(scyc == 18) {\r
         scyc = 9;  // wrap\r
         if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode\r
-         }\r
-       }\r
-       //dprintf("scyc: %i", scyc);\r
+      }\r
+    }\r
+    //dprintf("scyc: %i", scyc);\r
   }\r
   else if((sreg & 8) && (sreg & 2) && !(d&2)) {\r
     // we are started and SCL went low (falling edge)\r
     if(sreg & 0x20) {\r
-         // X24C02+\r
-         if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles\r
-         else if( (!(sreg&0x4000) && scyc > 27) || ((sreg&0x4000) && scyc > 18) ) {\r
+      // X24C02+\r
+      if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles\r
+      else if( (!(sreg&0x4000) && scyc > 27) || ((sreg&0x4000) && scyc > 18) ) {\r
         if(!(ssa&1)) {\r
           // data write\r
           unsigned char *pm=SRam.data+saddr;\r
@@ -208,18 +208,18 @@ PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)
       } else if(scyc > 9) {\r
         if(!(ssa&1)) {\r
           // we latch another addr bit\r
-                 saddr<<=1;\r
-                 if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
-                 saddr|=d&1;\r
+          saddr<<=1;\r
+          if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
+          saddr|=d&1;\r
           //if(scyc==17||scyc==26) dprintf("addr reg done: %x", saddr);\r
-               }\r
+        }\r
       } else {\r
-           // slave address\r
-               ssa<<=1; ssa|=d&1;\r
+        // slave address\r
+        ssa<<=1; ssa|=d&1;\r
         //if(scyc==8) dprintf("slave done: %x", ssa);\r
       }\r
-       } else {\r
-         // X24C01\r
+    } else {\r
+      // X24C01\r
       if(scyc == 9); // ACK cycle, do nothing\r
       else if(scyc > 9) {\r
         if(!(saddr&1)) {\r
@@ -237,7 +237,7 @@ PICO_INTERNAL void SRAMWriteEEPROM(unsigned int d) // ???? ??la (l=SCL, a=SDA)
         saddr<<=1; saddr|=d&1; saddr&=0xff;\r
         //if(scyc==8) dprintf("addr done: %x", saddr>>1);\r
       }\r
-       }\r
+    }\r
   }\r
 \r
   sreg &= ~3; sreg |= d&3; // remember SCL and SDA\r
@@ -265,17 +265,17 @@ PICO_INTERNAL_ASM unsigned int SRAMReadEEPROM(void)
     // started and first command word received\r
     shift = 17-scyc;\r
     if(sreg & 0x20) {\r
-         // X24C02+\r
+      // X24C02+\r
       if(ssa&1) {\r
         //dprintf("read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);\r
-           d = (SRam.data[saddr]>>shift)&1;\r
-         }\r
-       } else {\r
-         // X24C01\r
+        d = (SRam.data[saddr]>>shift)&1;\r
+      }\r
+    } else {\r
+      // X24C01\r
       if(saddr&1) {\r
-               d = (SRam.data[saddr>>1]>>shift)&1;\r
-         }\r
-       }\r
+        d = (SRam.data[saddr>>1]>>shift)&1;\r
+      }\r
+    }\r
   }\r
   //else dprintf("r ack");\r
 \r