-// 187 blocks, 12072 bytes
-// 14 IRAM blocks
+// SSP1601 to ARM recompiler
+
+// (c) Copyright 2008, Grazvydas "notaz" Ignotas
+// Free for non-commercial use.
#include "../../PicoInt.h"
#include "compiler.h"
-static unsigned int *block_table[0x5090/2];
-static unsigned int *block_table_iram[15][0x800/2];
-static unsigned int *tcache_ptr = NULL;
+#define u32 unsigned int
+
+static u32 *tcache_ptr = NULL;
static int nblocks = 0;
-static int iram_context = 0;
+static int n_in_ops = 0;
-#ifndef ARM
-#define DUMP_BLOCK 0x2018
-unsigned int tcache[512*1024];
-void regfile_load(void){}
-void regfile_store(void){}
-#endif
+extern ssp1601_t *ssp;
-#define EMBED_INTERPRETER
-#define ssp1601_reset ssp1601_reset_local
-#define ssp1601_run ssp1601_run_local
+#define rPC ssp->gr[SSP_PC].h
+#define rPMC ssp->gr[SSP_PMC]
-#define GET_PC() rPC
-#define GET_PPC_OFFS() (GET_PC()*2 - 2)
-#define SET_PC(d) { rPC = d; } /* must return to dispatcher after this */
-//#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
-//#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
-//#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
+#define SSP_FLAG_Z (1<<0xd)
+#define SSP_FLAG_N (1<<0xf)
+
+#ifndef ARM
+#define DUMP_BLOCK 0x0c9a
+u32 *ssp_block_table[0x5090/2];
+u32 *ssp_block_table_iram[15][0x800/2];
+u32 tcache[SSP_TCACHE_SIZE/4];
+void ssp_drc_next(void){}
+void ssp_drc_next_patch(void){}
+void ssp_drc_end(void){}
+#endif
-#include "ssp16.c"
#include "gen_arm.c"
// -----------------------------------------------------
-// ld d, s
-static void op00(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- PC = ((unsigned short *)(void *)&op) + 1; /* FIXME: needed for interpreter */
- if (op == 0) return; // nop
- if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
- // not sure. MAME claims that only hi word is transfered.
- read_P(); // update P
- rA32 = rP.v;
- }
- else
- {
- tmpv = REG_READ(op & 0x0f);
- REG_WRITE((op & 0xf0) >> 4, tmpv);
- }
-}
-
-// ld d, (ri)
-static void op01(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv);
-}
-
-// ld (ri), s
-static void op02(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv);
-}
-
-// ldi d, imm
-static void op04(unsigned int op, unsigned int imm)
-{
- REG_WRITE((op & 0xf0) >> 4, imm);
-}
-
-// ld d, ((ri))
-static void op05(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv);
-}
-
-// ldi (ri), imm
-static void op06(unsigned int op, unsigned int imm)
-{
- ptr1_write(op, imm);
-}
-
-// ld adr, a
-static void op07(unsigned int op, unsigned int imm)
-{
- ssp->RAM[op & 0x1ff] = rA;
-}
-
-// ld d, ri
-static void op09(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv);
-}
-
-// ld ri, s
-static void op0a(unsigned int op, unsigned int imm)
-{
- rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4);
-}
-
-// ldi ri, simm (also op0d op0e op0f)
-static void op0c(unsigned int op, unsigned int imm)
-{
- rIJ[(op>>8)&7] = op;
-}
-
-// call cond, addr
-static void op24(unsigned int op, unsigned int imm)
-{
- int cond = 0;
- do {
- COND_CHECK
- if (cond) { int new_PC = imm; write_STACK(GET_PC()); SET_PC(new_PC); }
- }
- while (0);
-}
-
-// ld d, (a)
-static void op25(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv);
-}
-
-// bra cond, addr
-static void op26(unsigned int op, unsigned int imm)
-{
- do
- {
- int cond = 0;
- COND_CHECK
- if (cond) SET_PC(imm);
- }
- while (0);
-}
-
-// mod cond, op
-static void op48(unsigned int op, unsigned int imm)
-{
- do
- {
- int cond = 0;
- COND_CHECK
- if (cond) {
- switch (op & 7) {
- case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
- case 3: rA32 <<= 1; break; // shl
- case 6: rA32 = -(signed int)rA32; break; // neg
- case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
- default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
- op&7, GET_PPC_OFFS());
- }
- UPD_ACC_ZN // ?
- }
- }
- while(0);
-}
-
-// mpys?
-static void op1b(unsigned int op, unsigned int imm)
-{
- read_P(); // update P
- rA32 -= rP.v; // maybe only upper word?
- UPD_ACC_ZN // there checking flags after this
- rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
- rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
-}
-
-// mpya (rj), (ri), b
-static void op4b(unsigned int op, unsigned int imm)
-{
- read_P(); // update P
- rA32 += rP.v; // confirmed to be 32bit
- UPD_ACC_ZN // ?
- rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
- rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
-}
-
-// mld (rj), (ri), b
-static void op5b(unsigned int op, unsigned int imm)
-{
- rA32 = 0;
- rST &= 0x0fff; // ?
- rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
- rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
-}
-
-// OP a, s
-static void op10(unsigned int op, unsigned int imm)
-{
- do
- {
- unsigned int tmpv;
- OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv);
- }
- while(0);
-}
-
-static void op30(unsigned int op, unsigned int imm)
-{
- do
- {
- unsigned int tmpv;
- OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv);
- }
- while(0);
-}
-
-static void op40(unsigned int op, unsigned int imm)
-{
- do
- {
- unsigned int tmpv;
- OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv);
- }
- while(0);
-}
-
-static void op50(unsigned int op, unsigned int imm)
-{
- do
- {
- unsigned int tmpv;
- OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv);
- }
- while(0);
-}
-
-static void op60(unsigned int op, unsigned int imm)
-{
- do
- {
- unsigned int tmpv;
- OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv);
- }
- while(0);
-}
-
-static void op70(unsigned int op, unsigned int imm)
+static int get_inc(int mode)
{
- do
- {
- unsigned int tmpv;
- OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv);
+ int inc = (mode >> 11) & 7;
+ if (inc != 0) {
+ if (inc != 7) inc--;
+ inc = 1 << inc; // 0 1 2 4 8 16 32 128
+ if (mode & 0x8000) inc = -inc; // decrement mode
}
- while(0);
-}
-
-// OP a, (ri)
-static void op11(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr1_read(op); OP_SUBA(tmpv);
-}
-
-static void op31(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr1_read(op); OP_CMPA(tmpv);
-}
-
-static void op41(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr1_read(op); OP_ADDA(tmpv);
-}
-
-static void op51(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr1_read(op); OP_ANDA(tmpv);
-}
-
-static void op61(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr1_read(op); OP_ORA (tmpv);
-}
-
-static void op71(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr1_read(op); OP_EORA(tmpv);
-}
-
-// OP a, adr
-static void op03(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv);
-}
-
-static void op13(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv);
-}
-
-static void op33(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv);
-}
-
-static void op43(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv);
-}
-
-static void op53(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv);
-}
-
-static void op63(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv);
-}
-
-static void op73(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv);
-}
-
-// OP a, imm
-static void op14(unsigned int op, unsigned int imm)
-{
- OP_SUBA(imm);
-}
-
-static void op34(unsigned int op, unsigned int imm)
-{
- OP_CMPA(imm);
-}
-
-static void op44(unsigned int op, unsigned int imm)
-{
- OP_ADDA(imm);
-}
-
-static void op54(unsigned int op, unsigned int imm)
-{
- OP_ANDA(imm);
-}
-
-static void op64(unsigned int op, unsigned int imm)
-{
- OP_ORA (imm);
-}
-
-static void op74(unsigned int op, unsigned int imm)
-{
- OP_EORA(imm);
-}
-
-// OP a, ((ri))
-static void op15(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr2_read(op); OP_SUBA(tmpv);
-}
-
-static void op35(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr2_read(op); OP_CMPA(tmpv);
-}
-
-static void op45(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr2_read(op); OP_ADDA(tmpv);
-}
-
-static void op55(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr2_read(op); OP_ANDA(tmpv);
-}
-
-static void op65(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr2_read(op); OP_ORA (tmpv);
+ return inc;
}
-static void op75(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = ptr2_read(op); OP_EORA(tmpv);
-}
-
-// OP a, ri
-static void op19(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = rIJ[IJind]; OP_SUBA(tmpv);
-}
-
-static void op39(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = rIJ[IJind]; OP_CMPA(tmpv);
-}
-
-static void op49(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = rIJ[IJind]; OP_ADDA(tmpv);
-}
-
-static void op59(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = rIJ[IJind]; OP_ANDA(tmpv);
-}
-
-static void op69(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = rIJ[IJind]; OP_ORA (tmpv);
-}
-
-static void op79(unsigned int op, unsigned int imm)
-{
- unsigned int tmpv;
- tmpv = rIJ[IJind]; OP_EORA(tmpv);
-}
-
-// OP simm
-static void op1c(unsigned int op, unsigned int imm)
-{
- OP_SUBA(op & 0xff);
-}
-
-static void op3c(unsigned int op, unsigned int imm)
-{
- OP_CMPA(op & 0xff);
-}
-
-static void op4c(unsigned int op, unsigned int imm)
-{
- OP_ADDA(op & 0xff);
-}
-
-static void op5c(unsigned int op, unsigned int imm)
-{
- OP_ANDA(op & 0xff);
-}
-
-static void op6c(unsigned int op, unsigned int imm)
-{
- OP_ORA (op & 0xff);
-}
-
-static void op7c(unsigned int op, unsigned int imm)
-{
- OP_EORA(op & 0xff);
-}
-
-typedef void (in_func)(unsigned int op, unsigned int imm);
-
-static in_func *in_funcs[0x80] =
-{
- op00, op01, op02, op03, op04, op05, op06, op07,
- NULL, op09, op0a, NULL, op0c, op0c, op0c, op0c,
- op10, op11, NULL, op13, op14, op15, NULL, NULL,
- NULL, op19, NULL, op1b, op1c, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, op24, op25, op26, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- op30, op31, NULL, op33, op34, op35, NULL, NULL,
- NULL, op39, NULL, NULL, op3c, NULL, NULL, NULL,
- op40, op41, NULL, op43, op44, op45, NULL, NULL,
- op48, op49, NULL, op4b, op4c, NULL, NULL, NULL,
- op50, op51, NULL, op53, op54, op55, NULL, NULL,
- NULL, op59, NULL, op5b, op5c, NULL, NULL, NULL,
- op60, op61, NULL, op63, op64, op65, NULL, NULL,
- NULL, op69, NULL, NULL, op6c, NULL, NULL, NULL,
- op70, op71, NULL, op73, op74, op75, NULL, NULL,
- NULL, op79, NULL, NULL, op7c, NULL, NULL, NULL,
-};
-
-
-static u32 ssp_pm_read(int reg)
+u32 ssp_pm_read(int reg)
{
u32 d = 0, mode;
{
ssp->pmac_read[reg] = rPMC.v;
ssp->emu_status &= ~SSP_PMC_SET;
- //elprintf("set PM%i %08x", ssp->pmac_read[reg]);
return 0;
}
- //elprintf("rd PM%i %08x", ssp->pmac_read[reg]);
// just in case
ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
return d;
}
-static void ssp_pm_write(u32 d, int reg)
+#define overwrite_write(dst, d) \
+{ \
+ if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
+ if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
+ if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
+ if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
+}
+
+void ssp_pm_write(u32 d, int reg)
{
unsigned short *dram;
int mode, addr;
if (mode & 0x0400) {
overwrite_write(dram[addr], d);
} else dram[addr] = d;
- ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
+ ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1;
}
else if ((mode & 0x47ff) == 0x001c) // IRAM
{
// -----------------------------------------------------
+// 14 IRAM blocks
static unsigned char iram_context_map[] =
{
0, 0, 0, 0, 1, 0, 0, 0, // 04
13,14, 0, 0, 0, 0, 0, 0 // 38 39
};
-static int get_iram_context(void)
+int ssp_get_iram_context(void)
{
unsigned char *ir = (unsigned char *)svp->iram_rom;
int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
val1 = iram_context_map[(val>>1)&0x3f];
if (val1 == 0) {
- printf("val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
+ elprintf(EL_ANOMALY, "svp: iram ctx val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
//debug_dump2file(name, svp->iram_rom, 0x800);
- exit(1);
+ //exit(1);
}
-// elprintf(EL_ANOMALY, "iram_context: %02i", val1);
return val1;
}
// -----------------------------------------------------
-/*
-enum {
- SSP_GR0, SSP_X, SSP_Y, SSP_A,
- SSP_ST, SSP_STACK, SSP_PC, SSP_P,
- SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
- SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
-};
-*/
+
/* regs with known values */
static struct
{
#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
#define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
-static void tr_unhandled(void)
+void tr_unhandled(void)
{
- FILE *f = fopen("tcache.bin", "wb");
- fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
- fclose(f);
- printf("unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
- exit(1);
+ //FILE *f = fopen("tcache.bin", "wb");
+ //fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
+ //fclose(f);
+ elprintf(EL_ANOMALY, "unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
+ //exit(1);
}
/* update P, if needed. Trashes r0 */
{
int i, ror = 0, reg;
int dirty = dirty_regb >> 8;
+ if ((dirty&7) == 7) {
+ emit_mov_const(A_COND_AL, 8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
+ dirty &= ~7;
+ }
+ if ((dirty&0x70) == 0x70) {
+ emit_mov_const(A_COND_AL, 9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
+ dirty &= ~0x70;
+ }
/* r0-r7 */
for (i = 0; dirty && i < 8; i++, dirty >>= 1)
{
hostreg_r[r] = -1;
}
-/* trashes r0 */
+/* trashes r1 */
static void tr_flush_dirty_pmcrs(void)
{
u32 i, val = (u32)-1;
EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
- printf("!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
+ elprintf(EL_ANOMALY, "!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
tr_unhandled();
}
}
hostreg_r[0] = hostreg_r[2] = -1;
}
+// check if AL is going to be used later in block
+static int tr_predict_al_need(void)
+{
+ int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
+
+ while (1)
+ {
+ op = PROGRAM(pc);
+ switch (op >> 9)
+ {
+ // ld d, s
+ case 0x00:
+ tmpv2 = (op >> 4) & 0xf; // dst
+ tmpv = op & 0xf; // src
+ if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
+ return 0;
+ break;
+
+ // ld (ri), s
+ case 0x02:
+ // ld ri, s
+ case 0x0a:
+ // OP a, s
+ case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
+ tmpv = op & 0xf; // src
+ if (tmpv == SSP_AL) // OP *, AL
+ return 1;
+ break;
+
+ case 0x04:
+ case 0x06:
+ case 0x14:
+ case 0x34:
+ case 0x44:
+ case 0x64:
+ case 0x74: pc++; break;
+
+ // call cond, addr
+ case 0x24:
+ // bra cond, addr
+ case 0x26:
+ // mod cond, op
+ case 0x48:
+ // mpys?
+ case 0x1b:
+ // mpya (rj), (ri), b
+ case 0x4b: return 1;
+
+ // mld (rj), (ri), b
+ case 0x5b: return 0; // cleared anyway
+
+ // and A, *
+ case 0x50:
+ tmpv = op & 0xf; // src
+ if (tmpv == SSP_AL) return 1;
+ case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
+ return 0;
+ }
+ pc++;
+ }
+}
+
+
/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
static int tr_cond_check(int op)
{
EOP_TST_IMM(6, 0, 8);
return f ? A_COND_NE : A_COND_EQ;
default:
- printf("unimplemented cond?\n");
+ elprintf(EL_ANOMALY, "unimplemented cond?\n");
tr_unhandled();
return 0;
}
static int tr_neg_cond(int cond)
{
switch (cond) {
- case A_COND_AL: printf("neg for AL?\n"); exit(1);
+ case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1);
case A_COND_EQ: return A_COND_NE;
case A_COND_NE: return A_COND_EQ;
case A_COND_MI: return A_COND_PL;
case A_COND_PL: return A_COND_MI;
- default: printf("bad cond for neg\n"); exit(1);
+ default: elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1);
}
return 0;
}
// -----------------------------------------------------
-// SSP_GR0, SSP_X, SSP_Y, SSP_A,
-// SSP_ST, SSP_STACK, SSP_PC, SSP_P,
//@ r4: XXYY
//@ r5: A
//@ r6: STACK and emu flags
static void tr_Y_to_r0(int op)
{
- // TODO..
if (hostreg_r[0] != (SSP_Y<<16)) {
EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
hostreg_r[0] = SSP_Y<<16;
tr_flush_dirty_ST();
EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
EOP_TST_REG_SIMPLE(0,0);
- EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // addeq r11, r11, #1024
+ EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1); // subeq r11, r11, #1024
EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
}
tr_flush_dirty_ST();
//tr_flush_dirty_pmcrs();
tr_mov16(0, reg);
- emit_call(ssp_pm_read);
+ emit_call(A_COND_AL, ssp_pm_read);
hostreg_clear();
}
static void tr_r0_to_A(int const_val)
{
- EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
- EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
- EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
+ if (tr_predict_al_need()) {
+ EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
+ EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
+ EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
+ }
+ else
+ EOP_MOV_REG_LSL(5, 0, 16);
TR_WRITE_R0_TO_REG(SSP_A);
}
static void tr_r0_to_PC(int const_val)
{
+/*
+ * do nothing - dispatcher will take care of this
EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
hostreg_r[1] = -1;
+*/
}
static void tr_r0_to_AL(int const_val)
static void tr_r0_to_PMX(int reg)
{
-#if 1
if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
{
known_regs.pmac_write[reg] = known_regs.pmc.v;
dirty_regb |= 1 << (25+reg);
return;
}
-#endif
-#if 1
+
if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
{
int mode, addr;
dirty_regb &= ~KRREG_PMC;
known_regb &= ~(1 << (25+reg));
dirty_regb &= ~(1 << (25+reg));
-#else
-tr_flush_dirty_pmcrs();
-hostreg_clear();
-known_regb &= ~KRREG_PMC;
-dirty_regb &= ~KRREG_PMC;
-known_regb &= ~(1 << (25+reg));
-dirty_regb &= ~(1 << (25+reg));
-#endif
-
// call the C code to handle this
tr_flush_dirty_ST();
//tr_flush_dirty_pmcrs();
tr_mov16(1, reg);
- emit_call(ssp_pm_write);
+ emit_call(A_COND_AL, ssp_pm_write);
hostreg_clear();
}
known_regb |= KRREG_PMC;
dirty_regb |= KRREG_PMC;
known_regs.emu_status |= SSP_PMC_SET;
+ n_in_ops++;
// check for possible reg programming
tmpv = PROGRAM(*pc);
dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
known_regs.emu_status &= ~SSP_PMC_SET;
(*pc)++;
+ n_in_ops++;
return 5;
}
known_regb |= 1 << SSP_ST;
dirty_regb &= ~KRREG_ST;
(*pc) += 3*2;
+ n_in_ops += 3;
return 4*2;
}
EOP_ORR_REG_LSR(0, 0, 0, 16);
tr_bank_write(0);
(*pc) += 2;
+ n_in_ops += 2;
return 3;
}
// -----------------------------------------------------
-static int translate_op(unsigned int op, int *pc, int imm)
+static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
{
u32 tmpv, tmpv2, tmpv3;
int ret = 0;
if (op == 0) { ret++; break; } // nop
tmpv = op & 0xf; // src
tmpv2 = (op >> 4) & 0xf; // dst
- //if (tmpv2 >= 8) return -1; // TODO
if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
tr_flush_dirty_P();
EOP_MOV_REG_SIMPLE(5, 10);
}
tr_read_funcs[tmpv](op);
tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
- if (tmpv2 == SSP_PC) ret |= 0x10000;
+ if (tmpv2 == SSP_PC) {
+ ret |= 0x10000;
+ *end_cond = -A_COND_AL;
+ }
ret++; break;
// ld d, (ri)
case 0x01: {
- // tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
int r = (op&3) | ((op>>6)&4);
int mod = (op>>2)&3;
tmpv = (op >> 4) & 0xf; // dst
ret = tr_detect_rotate(op, pc, imm);
if (ret > 0) break;
- if (tmpv >= 8) return -1; // TODO
if (tmpv != 0)
- tr_rX_read(r, mod);
- else tr_ptrr_mod(r, mod, 1, 1);
+ tr_rX_read(r, mod);
+ else {
+ int cnt = 1;
+ while (PROGRAM(*pc) == op) {
+ (*pc)++; cnt++; ret++;
+ n_in_ops++;
+ }
+ tr_ptrr_mod(r, mod, 1, cnt); // skip
+ }
tr_write_funcs[tmpv](-1);
- if (tmpv == SSP_PC) ret |= 0x10000;
+ if (tmpv == SSP_PC) {
+ ret |= 0x10000;
+ *end_cond = -A_COND_AL;
+ }
ret++; break;
}
tmpv = (op & 0xf0) >> 4; // dst
ret = tr_detect_pm0_block(op, pc, imm);
if (ret > 0) break;
- if (tmpv < 8)
- {
- tr_mov16(0, imm);
- tr_write_funcs[tmpv](imm);
- ret += 2; break;
- }
ret = tr_detect_set_pm(op, pc, imm);
if (ret > 0) break;
- if (tmpv == SSP_PC) ret |= 0x10000;
- return -1; /* TODO.. */
+ tr_mov16(0, imm);
+ tr_write_funcs[tmpv](imm);
+ if (tmpv == SSP_PC) {
+ ret |= 0x10000;
+ *jump_pc = imm;
+ }
+ ret += 2; break;
// ld d, ((ri))
case 0x05:
tmpv2 = (op >> 4) & 0xf; // dst
- if (tmpv2 >= 8) return -1; // TODO
tr_rX_read2(op);
tr_write_funcs[tmpv2](-1);
- if (tmpv2 == SSP_PC) ret |= 0x10000;
+ if (tmpv2 == SSP_PC) {
+ ret |= 0x10000;
+ *end_cond = -A_COND_AL;
+ }
ret += 3; break;
// ldi (ri), imm
int r;
r = (op&3) | ((op>>6)&4); // src
tmpv2 = (op >> 4) & 0xf; // dst
- if (tmpv2 >= 8) tr_unhandled();
if ((r&3) == 3) tr_unhandled();
if (known_regb & (1 << (r+8))) {
}
// ldi ri, simm
- case 0x0c ... 0x0f:
+ case 0x0c: case 0x0d: case 0x0e: case 0x0f:
tmpv = (op>>8)&7;
known_regs.r[tmpv] = op;
known_regb |= 1 << (tmpv + 8);
tcache_ptr = real_ptr;
}
tr_mov16_cond(tmpv, 0, imm);
- if (tmpv != A_COND_AL) {
+ if (tmpv != A_COND_AL)
tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
- }
tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ret |= 0x10000;
+ *end_cond = tmpv;
+ *jump_pc = imm;
ret += 2; break;
}
// ld d, (a)
case 0x25:
tmpv2 = (op >> 4) & 0xf; // dst
- if (tmpv2 >= 8) return -1; // TODO
-
tr_A_to_r0(op);
EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom
EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1
EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
hostreg_r[0] = hostreg_r[1] = -1;
tr_write_funcs[tmpv2](-1);
- if (tmpv2 == SSP_PC) ret |= 0x10000;
+ if (tmpv2 == SSP_PC) {
+ ret |= 0x10000;
+ *end_cond = -A_COND_AL;
+ }
ret += 3; break;
// bra cond, addr
case 0x26:
tmpv = tr_cond_check(op);
tr_mov16_cond(tmpv, 0, imm);
- if (tmpv != A_COND_AL) {
+ if (tmpv != A_COND_AL)
tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
- }
tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ret |= 0x10000;
+ *end_cond = tmpv;
+ *jump_pc = imm;
ret += 2; break;
// mod cond, op
tmpv = 1; // count
while (PROGRAM(*pc) == op && (op & 7) != 6) {
(*pc)++; tmpv++;
+ n_in_ops++;
}
if ((op&0xf0) != 0) // !always
tr_make_dirty_ST();
ret++; break;
}
+ n_in_ops++;
+
return ret;
}
-static void *translate_block(int pc)
+static void emit_block_prologue(void)
+{
+ // check if there are enough cycles..
+ // note: r0 must contain PC of current block
+ EOP_CMP_IMM(11,0,0); // cmp r11, #0
+ emit_call(A_COND_LE, ssp_drc_end);
+}
+
+/* cond:
+ * >0: direct (un)conditional jump
+ * <0: indirect jump
+ */
+static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
+{
+ if (cycles > 0xff) { elprintf(EL_ANOMALY, "large cycle count: %i\n", cycles); cycles = 0xff; }
+ EOP_SUB_IMM(11,11,0,cycles); // sub r11, r11, #cycles
+
+ if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
+ // indirect jump, or rom -> iram jump, must use dispatcher
+ emit_jump(A_COND_AL, ssp_drc_next);
+ }
+ else if (cond == A_COND_AL) {
+ u32 *target = (pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
+ if (target != NULL)
+ emit_jump(A_COND_AL, target);
+ else {
+ emit_jump(A_COND_AL, ssp_drc_next);
+ // cause the next block to be emitted over jump instrction
+ tcache_ptr--;
+ }
+ }
+ else {
+ u32 *target1 = (pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
+ u32 *target2 = (end_pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][end_pc] : ssp_block_table[end_pc];
+ if (target1 != NULL)
+ emit_jump(cond, target1);
+ else emit_call(cond, ssp_drc_next_patch);
+ if (target2 != NULL)
+ emit_jump(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
+ else emit_call(tr_neg_cond(cond), ssp_drc_next_patch);
+ }
+}
+
+void *ssp_translate_block(int pc)
{
unsigned int op, op1, imm, ccount = 0;
unsigned int *block_start;
- int ret, ret_prev = -1, tpc;
-
- // create .pool
- //*tcache_ptr++ = (u32) in_funcs; // -1 func pool
+ int ret, end_cond = A_COND_AL, jump_pc = -1;
- printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
+ //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
block_start = tcache_ptr;
known_regb = 0;
dirty_regb = KRREG_P;
for (; ccount < 100;)
{
- //printf(" insn #%i\n", icount);
op = PROGRAM(pc++);
op1 = op >> 9;
imm = (u32)-1;
if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
imm = PROGRAM(pc++); // immediate
- tpc = pc;
- ret = translate_op(op, &pc, imm);
+ ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
if (ret <= 0)
{
- tr_flush_dirty_prs();
- tr_flush_dirty_ST();
- tr_flush_dirty_pmcrs();
- known_regs.emu_status = 0;
-
- emit_mov_const(A_COND_AL, 0, op);
-
- // need immediate?
- if (imm != (u32)-1)
- emit_mov_const(A_COND_AL, 1, imm);
-
- // dump PC
- emit_pc_dump(pc);
-
- if (ret_prev > 0) emit_call(regfile_store);
- emit_call(in_funcs[op1]);
- emit_call(regfile_load);
-
- if (in_funcs[op1] == NULL) {
- printf("NULL func! op=%08x (%02x)\n", op, op1);
- exit(1);
- }
- ccount++;
- hostreg_clear();
- dirty_regb |= KRREG_P;
- known_regb = 0;
- }
- else
- {
- ccount += ret & 0xffff;
- if (ret & 0x10000) break;
+ elprintf(EL_ANOMALY, "NULL func! op=%08x (%02x)\n", op, op1);
+ //exit(1);
}
- ret_prev = ret;
+ ccount += ret & 0xffff;
+ if (ret & 0x10000) break;
+ }
+
+ if (ccount >= 100) {
+ end_cond = A_COND_AL;
+ jump_pc = pc;
+ emit_mov_const(A_COND_AL, 0, pc);
}
tr_flush_dirty_prs();
tr_flush_dirty_ST();
tr_flush_dirty_pmcrs();
- emit_block_epilogue(ccount + 1);
- *tcache_ptr++ = 0xffffffff; // end of block
- //printf(" %i inst\n", icount);
+ emit_block_epilogue(ccount, end_cond, jump_pc, pc);
- if (tcache_ptr - tcache > TCACHE_SIZE/4) {
- printf("tcache overflow!\n");
+ if (tcache_ptr - tcache > SSP_TCACHE_SIZE/4) {
+ elprintf(EL_ANOMALY, "tcache overflow!\n");
fflush(stdout);
exit(1);
}
// stats
nblocks++;
- //if (pc >= 0x400)
- printf("%i blocks, %i bytes\n", nblocks, (tcache_ptr - tcache)*4);
- //printf("%p %p\n", tcache_ptr, emit_block_epilogue);
+ //printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4,
+ // (double)(tcache_ptr - tcache) / (double)n_in_ops);
#ifdef DUMP_BLOCK
{
fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
fclose(f);
}
+ printf("dumped tcache.bin\n");
exit(0);
#endif
// -----------------------------------------------------
+static void ssp1601_state_load(void)
+{
+ ssp->drc.iram_dirty = 1;
+ ssp->drc.iram_context = 0;
+}
+
int ssp1601_dyn_startup(void)
{
- memset(tcache, 0, TCACHE_SIZE);
- memset(block_table, 0, sizeof(block_table));
- memset(block_table_iram, 0, sizeof(block_table_iram));
+ memset(tcache, 0, SSP_TCACHE_SIZE);
+ memset(ssp_block_table, 0, sizeof(ssp_block_table));
+ memset(ssp_block_table_iram, 0, sizeof(ssp_block_table_iram));
tcache_ptr = tcache;
- *tcache_ptr++ = 0xffffffff;
+ PicoLoadStateHook = ssp1601_state_load;
+
+ n_in_ops = 0;
#ifdef ARM
// hle'd blocks
- block_table[0x400] = (void *) ssp_hle_800;
+ ssp_block_table[0x800/2] = (void *) ssp_hle_800;
+ ssp_block_table[0x902/2] = (void *) ssp_hle_902;
+ ssp_block_table_iram[ 7][0x030/2] = (void *) ssp_hle_07_030;
+ ssp_block_table_iram[ 7][0x036/2] = (void *) ssp_hle_07_036;
+ ssp_block_table_iram[ 7][0x6d6/2] = (void *) ssp_hle_07_6d6;
+ ssp_block_table_iram[11][0x12c/2] = (void *) ssp_hle_11_12c;
+ ssp_block_table_iram[11][0x384/2] = (void *) ssp_hle_11_384;
+ ssp_block_table_iram[11][0x38a/2] = (void *) ssp_hle_11_38a;
#endif
-// TODO: rm
-{
-static unsigned short dummy = 0;
-PC = &dummy;
-}
return 0;
}
void ssp1601_dyn_reset(ssp1601_t *ssp)
{
- ssp1601_reset_local(ssp);
- ssp->drc.ptr_rom = (unsigned int) Pico.rom;
- ssp->drc.ptr_iram_rom = (unsigned int) svp->iram_rom;
- ssp->drc.ptr_dram = (unsigned int) svp->dram;
- ssp->drc.iram_dirty = 0;
+ ssp1601_reset(ssp);
+ ssp->drc.iram_dirty = 1;
+ ssp->drc.iram_context = 0;
+ // must do this here because ssp is not available @ startup()
+ ssp->drc.ptr_rom = (u32) Pico.rom;
+ ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
+ ssp->drc.ptr_dram = (u32) svp->dram;
+ ssp->drc.ptr_btable = (u32) ssp_block_table;
+ ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram;
+
+ // prevent new versions of IRAM from appearing
+ memset(svp->iram_rom, 0, 0x800);
}
void ssp1601_dyn_run(int cycles)
{
if (ssp->emu_status & SSP_WAIT_MASK) return;
- //{ printf("%i wait\n", Pico.m.frame_count); return; }
- //printf("%i %04x\n", Pico.m.frame_count, rPC<<1);
#ifdef DUMP_BLOCK
- rPC = DUMP_BLOCK >> 1;
+ ssp_translate_block(DUMP_BLOCK >> 1);
+#endif
+#ifdef ARM
+ ssp_drc_entry(cycles);
#endif
- while (cycles > 0)
- {
- int (*trans_entry)(void);
- if (rPC < 0x800/2)
- {
- if (ssp->drc.iram_dirty) {
- iram_context = get_iram_context();
- ssp->drc.iram_dirty--;
- }
- if (block_table_iram[iram_context][rPC] == NULL)
- block_table_iram[iram_context][rPC] = translate_block(rPC);
- trans_entry = (void *) block_table_iram[iram_context][rPC];
- }
- else
- {
- if (block_table[rPC] == NULL)
- block_table[rPC] = translate_block(rPC);
- trans_entry = (void *) block_table[rPC];
- }
-
- //printf("enter %04x\n", rPC<<1);
- cycles -= trans_entry();
- //printf("leave %04x\n", rPC<<1);
- }
-// debug_dump2file("tcache.bin", tcache, (tcache_ptr - tcache) << 1);
-// exit(1);
}
notaz.gp2x.de / picodrive.git / blobdiff