// 14 IRAM blocks
#include "../../PicoInt.h"
+#include "compiler.h"
-#define TCACHE_SIZE (256*1024)
static unsigned int *block_table[0x5090/2];
static unsigned int *block_table_iram[15][0x800/2];
-static unsigned int *tcache = NULL;
static unsigned int *tcache_ptr = NULL;
static int had_jump = 0;
static int nblocks = 0;
static int iram_context = 0;
+#ifndef ARM
+#define DUMP_BLOCK 0x84a
+unsigned int tcache[512*1024];
+void regfile_load(void){}
+void regfile_store(void){}
+#endif
+
#define EMBED_INTERPRETER
#define ssp1601_reset ssp1601_reset_local
#define ssp1601_run ssp1601_run_local
static void op00(unsigned int op, unsigned int imm)
{
unsigned int tmpv;
- PC = ((unsigned short *)&op) + 1; /* FIXME: needed for interpreter */
+ PC = ((unsigned short *)(void *)&op) + 1; /* FIXME: needed for interpreter */
if (op == 0) return; // nop
if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
// not sure. MAME claims that only hi word is transfered.
int cond = 0;
do {
COND_CHECK
- if (cond) { int new_PC = imm; write_STACK(GET_PC()); write_PC(new_PC); }
+ if (cond) { int new_PC = imm; write_STACK(GET_PC()); SET_PC(new_PC); }
}
while (0);
}
{
int cond = 0;
COND_CHECK
- if (cond) write_PC(imm);
+ if (cond) SET_PC(imm);
}
- while(0);
+ while (0);
}
// mod cond, op
return val1;
}
+// -----------------------------------------------------
+/*
+enum {
+ SSP_GR0, SSP_X, SSP_Y, SSP_A,
+ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
+ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
+ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
+};
+*/
+/* regs with known values */
+static struct
+{
+ ssp_reg_t gr[8];
+ unsigned char r[8];
+} const_regs;
+
+#define CRREG_X (1 << SSP_X)
+#define CRREG_Y (1 << SSP_Y)
+#define CRREG_A (1 << SSP_A) /* AH only */
+#define CRREG_ST (1 << SSP_ST)
+#define CRREG_STACK (1 << SSP_STACK)
+#define CRREG_PC (1 << SSP_PC)
+#define CRREG_P (1 << SSP_P)
+#define CRREG_PR0 (1 << 8)
+#define CRREG_PR4 (1 << 12)
+#define CRREG_AL (1 << 16)
+
+static u32 const_regb = 0; /* bitfield of known register values */
+static u32 dirty_regb = 0; /* known vals, which need to be flushed (only r0-r7) */
+
+/* known values of host regs.
+ * -1 - unknown
+ * 00000-0ffff - 16bit value
+ * 10000-1ffff - base reg (r7) + 16bit val
+ * 20000 - means reg (low) eq AH
+ */
+static int hostreg_r[4];
+
+static void hostreg_clear(void)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ hostreg_r[i] = -1;
+}
+
+/*static*/ void hostreg_ah_changed(void)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ if (hostreg_r[i] == 0x20000) hostreg_r[i] = -1;
+}
+
#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
+/* load 16bit val into host reg r0-r3. Nothing is trashed */
+static void tr_mov16(int r, int val)
+{
+ if (hostreg_r[r] != val) {
+ emit_mov_const(r, val);
+ hostreg_r[r] = val;
+ }
+}
+
+/* write dirty r0-r7 to host regs. Nothing is trashed */
+static void tr_flush_dirty(void)
+{
+ int i, ror = 0, reg;
+ dirty_regb >>= 8;
+ /* r0-r7 */
+ for (i = 0; dirty_regb && i < 8; i++, dirty_regb >>= 1)
+ {
+ if (!(dirty_regb&1)) continue;
+ switch (i&3) {
+ case 0: ror = 0; break;
+ case 1: ror = 24/2; break;
+ case 2: ror = 16/2; break;
+ }
+ reg = (i < 4) ? 8 : 9;
+ EOP_BIC_IMM(reg,reg,ror,0xff);
+ if (const_regs.r[i] != 0)
+ EOP_ORR_IMM(reg,reg,ror,const_regs.r[i]);
+ }
+}
+
+/* read bank word to r0 (MSW may contain trash). Thrashes r1. */
+static void tr_bank_read(int addr) /* word addr 0-0x1ff */
+{
+ if (addr&1) {
+ int breg = 7;
+ if (addr > 0x7f) {
+ if (hostreg_r[1] != (0x10000|((addr&0x180)<<1))) {
+ EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
+ hostreg_r[1] = 0x10000|((addr&0x180)<<1);
+ }
+ breg = 1;
+ }
+ EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1]
+ } else {
+ EOP_LDR_IMM(0,7,(addr&0x1ff)<<1); // ldr r0, [r1, (op&0x1ff)<<1]
+ }
+ hostreg_r[0] = -1;
+}
+
+/* write r0 to bank. Trashes r1. */
+static void tr_bank_write(int addr)
+{
+ int breg = 7;
+ if (addr > 0x7f) {
+ if (hostreg_r[1] != (0x10000|((addr&0x180)<<1))) {
+ EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
+ hostreg_r[1] = 0x10000|((addr&0x180)<<1);
+ }
+ breg = 1;
+ }
+ EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1]
+}
+
+/* handle RAM bank pointer modifiers. Nothing is trashed. */
+static void tr_ptrr_mod(int r, int mod, int need_modulo)
+{
+ int modulo = -1, modulo_shift = -1; /* unknown */
+
+ if (mod == 0) return;
+
+ if (!need_modulo || mod == 1) // +!
+ modulo_shift = 8;
+ else if (need_modulo && (const_regb & CRREG_ST)) {
+ modulo_shift = const_regs.gr[SSP_ST].h & 7;
+ if (modulo_shift == 0) modulo_shift = 8;
+ }
+
+ if (mod > 1 && modulo_shift == -1) { printf("need var modulo\n"); exit(1); }
+ modulo = (1 << modulo_shift) - 1;
+
+ if (const_regb & (1 << (r + 8))) {
+ if (mod == 2)
+ const_regs.r[r] = (const_regs.r[r] & ~modulo) | ((const_regs.r[r] - 1) & modulo);
+ else const_regs.r[r] = (const_regs.r[r] & ~modulo) | ((const_regs.r[r] + 1) & modulo);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
+ EOP_MOV_REG_ROR(reg,reg,ror);
+ // {add|sub} reg, reg, #1<<shift
+ EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, 1<<(8 - modulo_shift));
+ EOP_MOV_REG_ROR(reg,reg,32-ror);
+ }
+}
+
+// SSP_GR0, SSP_X, SSP_Y, SSP_A,
+// SSP_ST, SSP_STACK, SSP_PC, SSP_P,
+//@ r4: XXYY
+//@ r5: A
+//@ r6: STACK and emu flags
+//@ r7: SSP context
+//@ r10: P
+
+// write r0 to general reg handlers. Trashes r1
+static void tr_r0_unhandled(void)
+{
+ printf("unhandled\n");
+ exit(1);
+}
+
+static void tr_r0_to_GR0(void)
+{
+ // do nothing
+}
+
+static void tr_r0_to_X(void)
+{
+ EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
+ EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
+ EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
+}
+
+static void tr_r0_to_Y(void)
+{
+ EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
+ EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
+ EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
+}
+
+static void tr_r0_to_A(void)
+{
+ EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
+ EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsl #16 @ AL
+ EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
+ hostreg_r[0] = 0x20000;
+}
+
+static void tr_r0_to_ST(void)
+{
+ // VR doesn't need much accuracy here..
+ EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
+ EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
+ EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
+ hostreg_r[1] = -1;
+}
+
+static void tr_r0_to_STACK(void)
+{
+ // 448
+ EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
+ EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
+ EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #26
+ EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
+ EOP_ADD_IMM(6, 6, 24/2, 0x20); // add r6, r6, #1<<29
+ hostreg_r[1] = -1;
+}
+
+static void tr_r0_to_PC(void)
+{
+ EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
+ EOP_STR_IMM(0,7,0x400+6*4); // str r0, [r7, #(0x400+6*8)]
+ hostreg_r[1] = -1;
+}
+
+typedef void (tr_write_func)(void);
+
+static tr_write_func *tr_write_funcs[8] =
+{
+ tr_r0_to_GR0,
+ tr_r0_to_X,
+ tr_r0_to_Y,
+ tr_r0_to_A,
+ tr_r0_to_ST,
+ tr_r0_to_STACK,
+ tr_r0_to_PC,
+ tr_r0_unhandled
+};
+
+
+static int translate_op(unsigned int op, int *pc, int imm)
+{
+ u32 tmpv;
+ int ret = 0;
+
+ switch (op >> 9)
+ {
+ // ld d, s
+ case 0x00:
+ if (op == 0) { ret++; break; } // nop
+ break;
+
+ // ld a, adr
+ case 0x03:
+ tr_bank_read(op&0x1ff);
+ tr_r0_to_A();
+ const_regb &= ~CRREG_A;
+ hostreg_r[0] = 0x20000;
+ ret++; break;
+
+ // ldi d, imm
+ case 0x04:
+ tmpv = (op & 0xf0) >> 4;
+ if (tmpv < 8)
+ {
+ tr_mov16(0, imm);
+ tr_write_funcs[tmpv]();
+ const_regs.gr[tmpv].h = imm;
+ const_regb |= 1 << tmpv;
+ ret++; break;
+ }
+ else if (tmpv == 0xe && (PROGRAM(*pc) >> 9) == 4)
+ {
+ // programming PMC..
+ (*pc)++;
+ tmpv = imm | (PROGRAM((*pc)++) << 16);
+ emit_mov_const(0, tmpv);
+ EOP_LDR_IMM(1,7,0x484); // ldr r0, [r7, #0x484] // emu_status
+ EOP_STR_IMM(0,7,0x400+14*4); // PMC
+ // TODO: do this only on reads
+ if (tmpv == 0x187f04) { // fe08
+ EOP_LDR_IMM(0,7,0x490); // dram_ptr
+ EOP_ADD_IMM(0,0,24/2,0xfe); // add r0, r0, #0xfe00
+ EOP_LDRH_IMM(0,0,8); // ldrh r0, [r0, #8]
+ EOP_TST_REG_SIMPLE(0,0);
+ EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // add r11, r11, #1024
+ EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,SSP_WAIT_30FE08>>8); // orr r1, r1, #SSP_WAIT_30FE08
+ }
+ EOP_ORR_IMM(1,1,0,SSP_PMC_SET); // orr r1, r1, #SSP_PMC_SET
+ EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
+ hostreg_r[0] = hostreg_r[1] = -1;
+ ret += 2; break;
+ }
+ else
+ return -1; /* TODO.. */
+
+
+ // ldi (ri), imm
+ case 0x06:
+ // int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
+ tr_mov16(0, imm);
+ if ((op&3) == 3)
+ {
+ tmpv = (op>>2) & 3; // direct addressing
+ if (op & 0x100) {
+ if (hostreg_r[1] != 0x10200) {
+ EOP_ADD_IMM(1,7,30/2,0x200>>2); // add r1, r7, 0x200
+ hostreg_r[1] = 0x10200;
+ }
+ EOP_STRH_IMM(0,1,tmpv<<1); // str r0, [r1, {0,2,4,6}]
+ } else {
+ EOP_STRH_IMM(0,7,tmpv<<1); // str r0, [r7, {0,2,4,6}]
+ }
+ }
+ else
+ {
+ int r = (op&3) | ((op>>6)&4);
+ if (const_regb & (1 << (r + 8))) {
+ tr_bank_write(const_regs.r[r] | ((r < 4) ? 0 : 0x100));
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
+ if (r >= 4)
+ EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
+ if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
+ else EOP_ADD_REG_LSL(1,7,1,1);
+ EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
+ hostreg_r[1] = -1;
+ }
+ tr_ptrr_mod(r, (op>>2) & 3, 0);
+ }
+ ret++; break;
+
+ // ld adr, a
+ case 0x07:
+ if (hostreg_r[0] != 0x20000) {
+ EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ A
+ hostreg_r[0] = 0x20000;
+ }
+ tr_bank_write(op&0x1ff);
+ ret++; break;
+
+ // ldi ri, simm
+ case 0x0c ... 0x0f:
+ tmpv = (op>>8)&7;
+ const_regs.r[tmpv] = op;
+ const_regb |= 1 << (tmpv + 8);
+ dirty_regb |= 1 << (tmpv + 8);
+ ret++; break;
+ }
+
+ return ret;
+}
+
static void *translate_block(int pc)
{
- unsigned int op, op1, icount = 0;
+ unsigned int op, op1, imm, ccount = 0;
unsigned int *block_start;
+ int ret;
// create .pool
- *tcache_ptr++ = (u32) &g_cycles; // -3 g_cycles
- *tcache_ptr++ = (u32) &ssp->gr[SSP_PC].v; // -2 ptr to rPC
- *tcache_ptr++ = (u32) in_funcs; // -1 func pool
+ //*tcache_ptr++ = (u32) in_funcs; // -1 func pool
+ printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
block_start = tcache_ptr;
+ const_regb = dirty_regb = 0;
+ hostreg_clear();
emit_block_prologue();
- //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<1);
- for (;;)
+ for (; ccount < 100;)
{
- icount++;
+ //printf(" insn #%i\n", icount);
op = PROGRAM(pc++);
op1 = op >> 9;
+ imm = (u32)-1;
- emit_mov_const16(0, op);
+ if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
+ imm = PROGRAM(pc++); // immediate
- // need immediate?
- if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6) {
- emit_mov_const16(1, PROGRAM(pc++)); // immediate
- }
+ ret = translate_op(op, &pc, imm);
+ if (ret <= 0)
+ {
+ tr_flush_dirty();
+
+ emit_mov_const(0, op);
- // dump PC
- emit_pc_inc(block_start, pc);
+ // need immediate?
+ if (imm != (u32)-1)
+ emit_mov_const(1, imm);
- emit_call(block_start, op1);
+ // dump PC
+ emit_pc_dump(pc);
- if (in_funcs[op1] == NULL) {
- printf("NULL func! op=%08x (%02x)\n", op, op1);
- exit(1);
+ emit_interpreter_call(in_funcs[op1]);
+
+ if (in_funcs[op1] == NULL) {
+ printf("NULL func! op=%08x (%02x)\n", op, op1);
+ exit(1);
+ }
+ ccount++;
+ hostreg_clear();
}
+ else
+ ccount += ret;
+
if (op1 == 0x24 || op1 == 0x26 || // call, bra
((op1 == 0 || op1 == 1 || op1 == 4 || op1 == 5 || op1 == 9 || op1 == 0x25) &&
(op & 0xf0) == 0x60)) { // ld PC
}
}
- emit_block_epilogue(block_start, icount + 1);
+ tr_flush_dirty();
+ emit_block_epilogue(ccount + 1);
*tcache_ptr++ = 0xffffffff; // end of block
//printf(" %i inst\n", icount);
nblocks++;
//if (pc >= 0x400)
printf("%i blocks, %i bytes\n", nblocks, (tcache_ptr - tcache)*4);
+ //printf("%p %p\n", tcache_ptr, emit_block_epilogue);
-#if 0
+#ifdef DUMP_BLOCK
{
FILE *f = fopen("tcache.bin", "wb");
fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
}
exit(0);
#endif
+
+ handle_caches();
+
return block_start;
}
// -----------------------------------------------------
-int ssp1601_dyn_init(void)
+int ssp1601_dyn_startup(void)
{
- tcache = tcache_ptr = malloc(TCACHE_SIZE);
- if (tcache == NULL) {
- printf("oom\n");
- exit(1);
- }
- memset(tcache, 0, sizeof(TCACHE_SIZE));
+ memset(tcache, 0, TCACHE_SIZE);
memset(block_table, 0, sizeof(block_table));
memset(block_table_iram, 0, sizeof(block_table_iram));
+ tcache_ptr = tcache;
*tcache_ptr++ = 0xffffffff;
return 0;
void ssp1601_dyn_reset(ssp1601_t *ssp)
{
ssp1601_reset_local(ssp);
-}
-
-static void handle_caches()
-{
-#ifdef ARM
- extern void flush_inval_dcache(const void *start_addr, const void *end_addr);
- extern void flush_inval_icache(const void *start_addr, const void *end_addr);
- flush_inval_dcache(tcache, tcache_ptr);
- flush_inval_icache(tcache, tcache_ptr);
-#else
-#error wth
-#endif
+ ssp->rom_ptr = (unsigned int) Pico.rom;
+ ssp->iram_ptr = (unsigned int) svp->iram_rom;
+ ssp->dram_ptr = (unsigned int) svp->dram;
}
void ssp1601_dyn_run(int cycles)
{
+ if (ssp->emu_status & SSP_WAIT_MASK) return;
+ //{ printf("%i wait\n", Pico.m.frame_count); return; }
+ //printf("%i %04x\n", Pico.m.frame_count, rPC<<1);
+
+#ifdef DUMP_BLOCK
+ rPC = DUMP_BLOCK >> 1;
+#endif
while (cycles > 0)
{
- void (*trans_entry)(void);
+ int (*trans_entry)(void);
if (rPC < 0x800/2)
{
if (iram_dirty) {
had_jump = 0;
- //printf("enter @ %04x, PC=%04x\n", (PC - tcache)<<1, rPC<<1);
- g_cycles = 0;
- handle_caches();
- trans_entry();
- cycles -= g_cycles;
-/*
- if (!had_jump) {
- // no jumps
- if (pc_old < 0x800/2)
- rPC += (PC - block_table_iram[iram_context][pc_old]) - 1;
- else
- rPC += (PC - block_table[pc_old]) - 1;
- }
-*/
- //printf("end @ %04x, PC=%04x\n", (PC - tcache)<<1, rPC<<1);
-/*
- if (pc_old < 0x400) {
- // flush IRAM cache
- tcache_ptr = block_table[pc_old];
- block_table[pc_old] = NULL;
- nblocks--;
- }
- if (pc_old >= 0x400 && rPC < 0x400)
- {
- int i, crc = chksum_crc32(svp->iram_rom, 0x800);
- for (i = 0; i < 32; i++)
- if (iram_crcs[i] == crc) break;
- if (i == 32) {
- char name[32];
- for (i = 0; i < 32 && iram_crcs[i]; i++);
- iram_crcs[i] = crc;
- printf("%i IRAMs\n", i+1);
- sprintf(name, "ir%08x.bin", crc);
- debug_dump2file(name, svp->iram_rom, 0x800);
- }
- printf("CRC %08x %08x\n", crc, iram_id);
- }
-*/
+ //printf("enter %04x\n", rPC<<1);
+ cycles -= trans_entry();
+ //printf("leave %04x\n", rPC<<1);
}
// debug_dump2file("tcache.bin", tcache, (tcache_ptr - tcache) << 1);
// exit(1);
notaz.gp2x.de / picodrive.git / blobdiff