static int iram_context = 0;
#ifndef ARM
-#define DUMP_BLOCK 0x240a
+#define DUMP_BLOCK 0x08aa
unsigned int tcache[512*1024];
void regfile_load(void){}
void regfile_store(void){}
/* known vals, which need to be flushed
* (only ST, P, r0-r7)
* ST means flags are being held in ARM PSR
+ * P means that it needs to be recalculated
*/
static u32 dirty_regb = 0;
* -1 - unknown
* 000000-00ffff - 16bit value
* 100000-10ffff - base reg (r7) + 16bit val
- * 0r0000 - means reg (low) eq gr[r].h
+ * 0r0000 - means reg (low) eq gr[r].h, r != AL
*/
static int hostreg_r[4];
hostreg_r[i] = -1;
}
-// TODO
-/*static*/ void hostreg_ah_changed(void)
+static void hostreg_sspreg_changed(int sspreg)
{
int i;
for (i = 0; i < 4; i++)
- if (hostreg_r[i] == (SSP_A<<16)) hostreg_r[i] = -1;
+ if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
}
#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
-/* update P, if needed. Trashes r1 */
+static void tr_unhandled(void)
+{
+ FILE *f = fopen("tcache.bin", "wb");
+ fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
+ fclose(f);
+ printf("unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
+ exit(1);
+}
+
+/* update P, if needed. Trashes r0 */
static void tr_flush_dirty_P(void)
{
// TODO: const regs
if (!(dirty_regb & KRREG_P)) return;
EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
- EOP_MOV_REG_LSL( 1, 4, 16); // mov r1, r4, lsl #16
- EOP_MOV_REG_ASR( 1, 1, 15); // mov r1, r1, asr #15
- EOP_MUL(10, 1, 10); // mul r10, r1, r10
+ EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16
+ EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15
+ EOP_MUL(10, 0, 10); // mul r10, r0, r10
dirty_regb &= ~KRREG_P;
+ hostreg_r[0] = -1;
}
-/* write dirty r0-r7 to host regs. Nothing is trashed */
-static void tr_flush_dirty_pr(void)
+/* write dirty pr to host reg. Nothing is trashed */
+static void tr_flush_dirty_pr(int r)
+{
+ int ror = 0, reg;
+
+ if (!(dirty_regb & (1 << (r+8)))) return;
+
+ switch (r&3) {
+ case 0: ror = 0; break;
+ case 1: ror = 24/2; break;
+ case 2: ror = 16/2; break;
+ }
+ reg = (r < 4) ? 8 : 9;
+ EOP_BIC_IMM(reg,reg,ror,0xff);
+ if (known_regs.r[r] != 0)
+ EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
+ dirty_regb &= ~(1 << (r+8));
+}
+
+/* write all dirty pr0-pr7 to host regs. Nothing is trashed */
+static void tr_flush_dirty_prs(void)
{
int i, ror = 0, reg;
int dirty = dirty_regb >> 8;
dirty_regb &= ~0xff00;
}
-/* fush ARM PSR to r6. Trashes r0 */
+/* write dirty pr and "forget" it. Nothing is trashed. */
+static void tr_release_pr(int r)
+{
+ tr_flush_dirty_pr(r);
+ known_regb &= ~(1 << (r+8));
+}
+
+/* fush ARM PSR to r6. Trashes r1 */
static void tr_flush_dirty_ST(void)
{
if (!(dirty_regb & KRREG_ST)) return;
EOP_BIC_IMM(6,6,0,0x0f);
- EOP_MRS(0);
- EOP_ORR_REG_LSR(6,6,0,28);
+ EOP_MRS(1);
+ EOP_ORR_REG_LSR(6,6,1,28);
dirty_regb &= ~KRREG_ST;
- hostreg_r[0] = -1;
+ hostreg_r[1] = -1;
+}
+
+/* inverse of above. Trashes r1 */
+static void tr_make_dirty_ST(void)
+{
+ if (dirty_regb & KRREG_ST) return;
+ if (known_regb & KRREG_ST) {
+ int flags = 0;
+ if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
+ if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
+ EOP_MSR_IMM(4/2, flags);
+ } else {
+ EOP_MOV_REG_LSL(1, 6, 28);
+ EOP_MSR_REG(1);
+ hostreg_r[1] = -1;
+ }
+ dirty_regb |= KRREG_ST;
}
/* load 16bit val into host reg r0-r3. Nothing is trashed */
hostreg_r[r] = -1;
}
-/* read bank word to r0. Thrashes r1. */
+/* read bank word to r0 (upper bits zero). Thrashes r1. */
static void tr_bank_read(int addr) /* word addr 0-0x1ff */
{
int breg = 7;
EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1]
}
-/* handle RAM bank pointer modifiers. Nothing is trashed. */
-static void tr_ptrr_mod(int r, int mod, int need_modulo)
+/* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
+static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
{
int modulo_shift = -1; /* unknown */
if (modulo_shift == 0) modulo_shift = 8;
}
- if (mod > 1 && modulo_shift == -1) {
-/* TODO
+ if (modulo_shift == -1)
+ {
int reg = (r < 4) ? 8 : 9;
- int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
- EOP_MOV_REG_ROR(reg,reg,ror);
- // {add|sub} reg, reg, #1<<shift
- EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, 1<<(8 - modulo_shift));
- EOP_MOV_REG_ROR(reg,reg,32-ror);
-*/
-
- printf("need var modulo\n"); exit(1);
+ tr_release_pr(r);
+ if (dirty_regb & KRREG_ST) {
+ // avoid flushing ARM flags
+ EOP_AND_IMM(1, 6, 0, 0x70);
+ EOP_SUB_IMM(1, 1, 0, 0x10);
+ EOP_AND_IMM(1, 1, 0, 0x70);
+ EOP_ADD_IMM(1, 1, 0, 0x10);
+ } else {
+ EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70
+ EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
+ }
+ EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4
+ EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8
+ EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000
+ if (r&3)
+ EOP_ADD_IMM(1, 1, 0, (r&3)*8); // add r1, r1, #(r&3)*8
+ EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
+ if (mod == 2)
+ EOP_SUB_REG2_LSL(reg,reg,3,2); // sub reg, reg, #0x01000000 << r2
+ else EOP_ADD_REG2_LSL(reg,reg,3,2);
+ EOP_RSB_IMM(1, 1, 0, 32); // rsb r1, r1, #32
+ EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
+ hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
}
else if (known_regb & (1 << (r + 8)))
{
int modulo = (1 << modulo_shift) - 1;
if (mod == 2)
- known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - 1) & modulo);
- else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + 1) & modulo);
+ known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
+ else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
}
else
{
int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
EOP_MOV_REG_ROR(reg,reg,ror);
// {add|sub} reg, reg, #1<<shift
- EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, 1<<(8 - modulo_shift));
+ EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
EOP_MOV_REG_ROR(reg,reg,32-ror);
}
}
/* handle writes r0 to (rX). Trashes r1.
* fortunately we can ignore modulo increment modes for writes. */
-static void tr_rX_write1(int op)
+static void tr_rX_write(int op)
{
if ((op&3) == 3)
{
EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
hostreg_r[1] = -1;
}
- tr_ptrr_mod(r, (op>>2) & 3, 0);
+ tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
}
}
+/* read (rX) to r0. Trashes r1-r3. */
+static void tr_rX_read(int r, int mod)
+{
+ if ((r&3) == 3)
+ {
+ tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
+ }
+ else
+ {
+ if (known_regb & (1 << (r + 8))) {
+ tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
+ if (r >= 4)
+ EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
+ if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
+ else EOP_ADD_REG_LSL(1,7,1,1);
+ EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
+ hostreg_r[0] = hostreg_r[1] = -1;
+ }
+ tr_ptrr_mod(r, mod, 1, 1);
+ }
+}
+
+/* read ((rX)) to r0. Trashes r1,r2. */
+static void tr_rX_read2(int op)
+{
+ int r = (op&3) | ((op>>6)&4); // src
+
+ if ((r&3) == 3) {
+ tr_bank_read((op&0x100) | ((op>>2)&3));
+ } else if (known_regb & (1 << (r+8))) {
+ tr_bank_read((op&0x100) | known_regs.r[r]);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
+ if (r >= 4)
+ EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
+ if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
+ else EOP_ADD_REG_LSL(1,7,1,1);
+ EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
+ }
+ EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
+ EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
+ EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
+ if ((r&3) == 3) {
+ tr_bank_write((op&0x100) | ((op>>2)&3));
+ } else if (known_regb & (1 << (r+8))) {
+ tr_bank_write((op&0x100) | known_regs.r[r]);
+ } else {
+ EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
+ hostreg_r[1] = -1;
+ }
+ EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
+ hostreg_r[0] = hostreg_r[2] = -1;
+}
+
/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
static int tr_cond_check(int op)
{
- int f = op & 0x100;
+ int f = (op & 0x100) >> 8;
switch (op&0xf0) {
case 0x00: return A_COND_AL; /* always true */
case 0x50: /* Z matches f(?) bit */
return f ? A_COND_NE : A_COND_EQ;
default:
printf("unimplemented cond?\n");
- exit(1);
+ tr_unhandled();
return 0;
}
}
// write r0 to general reg handlers. Trashes r1
-static void tr_unhandled(void)
-{
- printf("unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
- exit(1);
+#define TR_WRITE_R0_TO_REG(reg) \
+{ \
+ hostreg_sspreg_changed(reg); \
+ hostreg_r[0] = (reg)<<16; \
+ if (const_val != -1) { \
+ known_regs.gr[reg].h = const_val; \
+ known_regb |= 1 << (reg); \
+ } else { \
+ known_regb &= ~(1 << (reg)); \
+ } \
}
-static void tr_r0_to_GR0(void)
+static void tr_r0_to_GR0(int const_val)
{
// do nothing
}
-static void tr_r0_to_X(void)
+static void tr_r0_to_X(int const_val)
{
EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
- dirty_regb |= KRREG_P; // touching X or Y makes P dirty.
- hostreg_r[0] = SSP_X<<16;
+ dirty_regb |= KRREG_P; // touching X or Y makes P dirty.
+ TR_WRITE_R0_TO_REG(SSP_X);
}
-static void tr_r0_to_Y(void)
+static void tr_r0_to_Y(int const_val)
{
EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
dirty_regb |= KRREG_P;
- hostreg_r[0] = SSP_Y<<16;
+ TR_WRITE_R0_TO_REG(SSP_Y);
}
-static void tr_r0_to_A(void)
+static void tr_r0_to_A(int const_val)
{
EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
- hostreg_r[0] = SSP_A<<16;
+ TR_WRITE_R0_TO_REG(SSP_A);
}
-static void tr_r0_to_ST(void)
+static void tr_r0_to_ST(int const_val)
{
// VR doesn't need much accuracy here..
EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
+ TR_WRITE_R0_TO_REG(SSP_ST);
hostreg_r[1] = -1;
+ dirty_regb &= ~KRREG_ST;
}
-static void tr_r0_to_STACK(void)
+static void tr_r0_to_STACK(int const_val)
{
// 448
EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
hostreg_r[1] = -1;
}
-static void tr_r0_to_PC(void)
+static void tr_r0_to_PC(int const_val)
{
EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
hostreg_r[1] = -1;
}
-typedef void (tr_write_func)(void);
+typedef void (tr_write_func)(int const_val);
static tr_write_func *tr_write_funcs[8] =
{
tr_r0_to_ST,
tr_r0_to_STACK,
tr_r0_to_PC,
- tr_unhandled
+ (tr_write_func *)tr_unhandled
};
+static void tr_mac_load_XY(int op)
+{
+ tr_rX_read(op&3, (op>>2)&3); // X
+ EOP_MOV_REG_LSL(4, 0, 16);
+ tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
+ EOP_ORR_REG_SIMPLE(4, 0);
+ dirty_regb |= KRREG_P;
+ hostreg_sspreg_changed(SSP_X);
+ hostreg_sspreg_changed(SSP_Y);
+ known_regb &= ~KRREG_X;
+ known_regb &= ~KRREG_Y;
+}
+
+static int tr_aop_ssp2arm(int op)
+{
+ switch (op) {
+ case 1: return A_OP_SUB;
+ case 3: return A_OP_CMP;
+ case 4: return A_OP_ADD;
+ case 5: return A_OP_AND;
+ case 6: return A_OP_ORR;
+ case 7: return A_OP_EOR;
+ }
+
+ tr_unhandled();
+ return 0;
+}
static int translate_op(unsigned int op, int *pc, int imm)
{
- u32 tmpv, tmpv2;
+ u32 tmpv, tmpv2, tmpv3;
int ret = 0;
known_regs.gr[SSP_PC].h = *pc;
if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
tr_flush_dirty_P();
EOP_MOV_REG_SIMPLE(5, 10);
+ hostreg_sspreg_changed(SSP_A); \
known_regb &= ~(KRREG_A|KRREG_AL);
ret++; break;
}
tr_read_funcs[tmpv]();
- tr_write_funcs[tmpv2]();
- if (known_regb & (1 << tmpv)) {
- known_regs.gr[tmpv2].h = known_regs.gr[tmpv].h;
- known_regb |= 1 << tmpv2;
- } else
- known_regb &= ~(1 << tmpv2);
+ tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
ret++; break;
// ld d, (ri)
- //case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+ case 0x01: {
+ // tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+ int r = (op&3) | ((op>>6)&4);
+ int mod = (op>>2)&3;
+ tmpv = (op >> 4) & 0xf; // dst
+ if (tmpv >= 8) return -1; // TODO
+ if (tmpv != 0)
+ tr_rX_read(r, mod);
+ else tr_ptrr_mod(r, mod, 1, 1);
+ tr_write_funcs[tmpv](-1);
+ ret++; break;
+ }
// ld (ri), s
case 0x02:
tmpv = (op >> 4) & 0xf; // src
if (tmpv >= 8) return -1; // TODO
tr_read_funcs[tmpv]();
- tr_rX_write1(op);
+ tr_rX_write(op);
ret++; break;
// ld a, adr
case 0x03:
tr_bank_read(op&0x1ff);
- tr_r0_to_A();
- known_regb &= ~KRREG_A;
- hostreg_r[0] = SSP_A<<16;
+ tr_r0_to_A(-1);
ret++; break;
// ldi d, imm
if (tmpv < 8)
{
tr_mov16(0, imm);
- tr_write_funcs[tmpv]();
- known_regs.gr[tmpv].h = imm;
- known_regb |= 1 << tmpv;
+ tr_write_funcs[tmpv](imm);
ret += 2; break;
}
else if (tmpv == 0xe && (PROGRAM(*pc) >> 9) == 4)
tmpv = imm | (PROGRAM((*pc)++) << 16);
ret += 2;
emit_mov_const(A_COND_AL, 0, tmpv);
- EOP_LDR_IMM(1,7,0x484); // ldr r0, [r7, #0x484] // emu_status
+ EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
EOP_STR_IMM(0,7,0x400+14*4); // PMC
// reads on fe06, fe08; next op is ld -,
if ((tmpv == 0x187f03 || tmpv == 0x187f04) && (PROGRAM(*pc) & 0xfff0) == 0)
int flag = (tmpv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
tr_flush_dirty_ST();
EOP_LDR_IMM(0,7,0x490); // dram_ptr
- EOP_ADD_IMM(0,0,24/2,0xfe); // add r0, r0, #0xfe00
- EOP_LDRH_IMM(0,0,8); // ldrh r0, [r0, #8]
+ EOP_ADD_IMM(0,0,24/2,0xfe); // add r0, r0, #0xfe00
+ EOP_LDRH_IMM(0,0,(tmpv == 0x187f03) ? 6 : 8); // ldrh r0, [r0, #8]
EOP_TST_REG_SIMPLE(0,0);
EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // add r11, r11, #1024
EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orr r1, r1, #SSP_WAIT_30FE08
return -1; /* TODO.. */
// ld d, ((ri))
- case 0x05: {
- int r;
- r = (op&3) | ((op>>6)&4); // src
+ case 0x05:
tmpv2 = (op >> 4) & 0xf; // dst
if (tmpv2 >= 8) return -1; // TODO
-
- if ((r&3) == 3) {
- tr_bank_read((op&0x100) | ((op>>2)&3));
- } else if (known_regb & (1 << (r+8))) {
- tr_bank_read((op&0x100) | known_regs.r[r]);
- } else {
- int reg = (r < 4) ? 8 : 9;
- int ror = ((4 - (r&3))*8) & 0x1f;
- EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
- if (r >= 4)
- EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
- if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
- else EOP_ADD_REG_LSL(1,7,1,1);
- EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
- }
- EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
- EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
- EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
- if ((r&3) == 3) {
- tr_bank_write((op&0x100) | ((op>>2)&3));
- } else if (known_regb & (1 << (r+8))) {
- tr_bank_write((op&0x100) | known_regs.r[r]);
- } else {
- EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
- hostreg_r[1] = -1;
- }
- EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r0]
- hostreg_r[0] = hostreg_r[2] = -1;
- known_regb &= ~(1 << tmpv2);
- tr_write_funcs[tmpv2]();
- ret += 3; break; /* should certainly take > 1 */
- }
+ tr_rX_read2(op);
+ tr_write_funcs[tmpv2](-1);
+ ret += 3; break;
// ldi (ri), imm
case 0x06:
tr_mov16(0, imm);
- tr_rX_write1(op);
+ tr_rX_write(op);
ret += 2; break;
// ld adr, a
case 0x07:
- if (hostreg_r[0] != (SSP_A<<16)) {
- EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ A
- hostreg_r[0] = SSP_A<<16;
- }
+ tr_A_to_r0();
tr_bank_write(op&0x1ff);
ret++; break;
if (known_regb & (1 << (r+8))) {
tr_mov16(0, known_regs.r[r]);
- known_regs.gr[tmpv2].h = known_regs.r[r];
- known_regb |= 1 << tmpv2;
+ tr_write_funcs[tmpv2](known_regs.r[r]);
} else {
int reg = (r < 4) ? 8 : 9;
if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
hostreg_r[0] = -1;
- known_regb &= ~(1 << tmpv2);
+ tr_write_funcs[tmpv2](-1);
}
- tr_write_funcs[tmpv2]();
ret++; break;
}
ret++; break;
// call cond, addr
- case 0x24:
- tr_mov16(0, *pc);
- tr_r0_to_STACK();
+ case 0x24: {
+ u32 *jump_op = NULL;
tmpv = tr_cond_check(op);
+ if (tmpv != A_COND_AL) {
+ jump_op = tcache_ptr;
+ EOP_MOV_IMM(0, 0, 0); // placeholder for branch
+ }
+ tr_mov16(0, *pc);
+ tr_r0_to_STACK(*pc);
+ if (tmpv != A_COND_AL) {
+ u32 *real_ptr = tcache_ptr;
+ tcache_ptr = jump_op;
+ EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
+ tcache_ptr = real_ptr;
+ }
tr_mov16_cond(tmpv, 0, imm);
if (tmpv != A_COND_AL) {
tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
}
- tr_r0_to_PC();
+ tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ret += 2; break;
+ }
// ld d, (a)
case 0x25:
EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1
EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
hostreg_r[0] = hostreg_r[1] = -1;
- known_regb &= ~(1 << tmpv2);
- tr_write_funcs[tmpv2]();
+ tr_write_funcs[tmpv2](-1);
ret += 3; break;
// bra cond, addr
if (tmpv != A_COND_AL) {
tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
}
- tr_r0_to_PC();
+ tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ret += 2; break;
+ // mod cond, op
+ case 0x48: {
+ // check for repeats of this op
+ tmpv = 1; // count
+ while (PROGRAM(*pc) == op && (op & 7) != 6) {
+ (*pc)++; tmpv++;
+ }
+ if ((op&0xf0) != 0) // !always
+ tr_make_dirty_ST();
+
+ tmpv2 = tr_cond_check(op);
+ switch (op & 7) {
+ case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
+ case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
+ case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
+ case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor r1, r5, r5, asr #31
+ EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
+ hostreg_r[1] = -1; break; // abs
+ default: tr_unhandled();
+ }
+
+ hostreg_sspreg_changed(SSP_A);
+ dirty_regb |= KRREG_ST;
+ known_regb &= ~KRREG_ST;
+ known_regb &= ~(KRREG_A|KRREG_AL);
+ ret += tmpv; break;
+ }
-/*
// mpys?
case 0x1b:
- read_P(); // update P
- rA32 -= rP.v; // maybe only upper word?
- UPD_ACC_ZN // there checking flags after this
- rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
- rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
- break;
+ tr_flush_dirty_P();
+ tr_mac_load_XY(op);
+ tr_make_dirty_ST();
+ EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
// mpya (rj), (ri), b
case 0x4b:
- read_P(); // update P
- rA32 += rP.v; // confirmed to be 32bit
- UPD_ACC_ZN // ?
- rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
- rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
- break;
+ tr_flush_dirty_P();
+ tr_mac_load_XY(op);
+ tr_make_dirty_ST();
+ EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
// mld (rj), (ri), b
case 0x5b:
- EOP_MOV_IMM(5, 0, 0); // mov r5, #0
- known_regs.r[SSP_A].v = 0;
+ EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
+ hostreg_sspreg_changed(SSP_A);
+ known_regs.gr[SSP_A].v = 0;
known_regb |= (KRREG_A|KRREG_AL);
- EOP_BIC_IMM(6, 6, 0, 0x0f); // bic r6, r6, 0xf // flags
- EOP_BIC_IMM(6, 6, 0, 0x04); // bic r6, r6, 4 // set Z
- // TODO
+ dirty_regb |= KRREG_ST;
+ tr_mac_load_XY(op);
+ ret++; break;
+
+ // OP a, s
+ case 0x10:
+ case 0x30:
+ case 0x40:
+ case 0x50:
+ case 0x60:
+ case 0x70:
+ tmpv = op & 0xf; // src
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ if (tmpv >= 8) return -1; // TODO
+ if (tmpv == SSP_P) {
+ tr_flush_dirty_P();
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
+ } else if (tmpv == SSP_A) {
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
+ } else {
+ tr_read_funcs[tmpv]();
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
+ }
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
+
+ // OP a, (ri)
+ case 0x11:
+ case 0x31:
+ case 0x41:
+ case 0x51:
+ case 0x61:
+ case 0x71:
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
+
+ // OP a, adr
+ case 0x13:
+ case 0x33:
+ case 0x43:
+ case 0x53:
+ case 0x63:
+ case 0x73:
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ tr_bank_read(op&0x1ff);
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
+
+ // OP a, imm
+ case 0x14:
+ case 0x34:
+ case 0x44:
+ case 0x54:
+ case 0x64:
+ case 0x74:
+ tmpv = (op & 0xf0) >> 4;
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ tr_mov16(0, imm);
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret += 2; break;
+
+ // OP a, ((ri))
+ case 0x15:
+ case 0x35:
+ case 0x45:
+ case 0x55:
+ case 0x65:
+ case 0x75:
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ tr_rX_read2(op);
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret += 3; break;
+
+ // OP a, ri
+ case 0x19:
+ case 0x39:
+ case 0x49:
+ case 0x59:
+ case 0x69:
+ case 0x79: {
+ int r;
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ r = (op&3) | ((op>>6)&4); // src
+ if ((r&3) == 3) tr_unhandled();
+
+ if (known_regb & (1 << (r+8))) {
+ EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
+ EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
+ hostreg_r[0] = -1;
+ }
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
+ }
+
+ // OP simm
+ case 0x1c:
+ case 0x3c:
+ case 0x4c:
+ case 0x5c:
+ case 0x6c:
+ case 0x7c:
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
ret++; break;
-*/
}
return ret;
ret = translate_op(op, &pc, imm);
if (ret <= 0)
{
- tr_flush_dirty_pr();
+ tr_flush_dirty_prs();
+ tr_flush_dirty_ST();
emit_mov_const(A_COND_AL, 0, op);
ret_prev = ret;
}
- tr_flush_dirty_pr();
+ tr_flush_dirty_prs();
+ tr_flush_dirty_ST();
emit_block_epilogue(ccount + 1);
*tcache_ptr++ = 0xffffffff; // end of block
//printf(" %i inst\n", icount);
tcache_ptr = tcache;
*tcache_ptr++ = 0xffffffff;
+// TODO: rm
+{
+static unsigned short dummy = 0;
+PC = &dummy;
+}
return 0;
}
notaz.gp2x.de / picodrive.git / blobdiff