UIQ3 bugfixes, SVP drc indirect jumps, stuff

[picodrive.git] / Pico / carthw / svp / gen_arm.c

diff --git a/Pico/carthw/svp/gen_arm.c b/Pico/carthw/svp/gen_arm.c
index bbf2807..56018a7 100644 (file)
--- a/Pico/carthw/svp/gen_arm.c
+++ b/Pico/carthw/svp/gen_arm.c
@@ -1,3 +1,8 @@
+// Basic macros to emit ARM instructions and some utils
+
+// (c) Copyright 2008, Grazvydas "notaz" Ignotas
+// Free for non-commercial use.
+
 #define EMIT(x) *tcache_ptr++ = x
 
 #define A_R4M  (1 << 4)
@@ -15,6 +20,7 @@
 #define A_COND_NE 0x1
 #define A_COND_MI 0x4
 #define A_COND_PL 0x5
+#define A_COND_LE 0xd
 
 /* addressing mode 1 */
 #define A_AM1_LSL 0
@@ -52,6 +58,7 @@
 #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
 #define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
 #define EOP_TST_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
+#define EOP_CMP_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
 #define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
 
 #define EOP_MOV_REG(s,   rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
@@ -171,58 +178,56 @@ static void emit_mov_const(int cond, int d, unsigned int val)
                EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 0, val&0xff);
 }
 
-/*
-static void check_offset_12(unsigned int val)
-{
-       if (!(val & ~0xfff)) return;
-       printf("offset_12 overflow %04x\n", val);
-       exit(1);
-}
-*/
-
-static void check_offset_24(int val)
+static int is_offset_24(int val)
 {
-       if (val >= (int)0xff000000 && val <= 0x00ffffff) return;
-       printf("offset_24 overflow %08x\n", val);
-       exit(1);
+       if (val >= (int)0xff000000 && val <= 0x00ffffff) return 1;
+       return 0;
 }
 
-static void emit_call(void *target)
+static int emit_xbranch(int cond, void *target, int is_call)
 {
        int val = (unsigned int *)target - tcache_ptr - 2;
-       check_offset_24(val);
+       int direct = is_offset_24(val);
+       u32 *start_ptr = tcache_ptr;
 
-       EOP_BL(val & 0xffffff);                 // bl target
-}
+       if (direct)
+       {
+               EOP_C_B(cond,is_call,val & 0xffffff);           // b, bl target
+       }
+       else
+       {
+#ifdef __EPOC32__
+//             elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
+               if (is_call)
+                       EOP_ADD_IMM(14,15,0,8);                 // add lr,pc,#8
+               EOP_C_AM2_IMM(cond,1,0,1,15,15,0);              // ldrcc pc,[pc]
+               EOP_MOV_REG_SIMPLE(15,15);                      // mov pc, pc
+               EMIT((u32)target);
+#else
+               // should never happen
+               elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
+               exit(1);
+#endif
+       }
 
-static void emit_block_prologue(void)
-{
-       // stack regs
-       EOP_STMFD_ST(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M); // stmfd r13!, {r4-r11,lr}
-       emit_call(regfile_load);
-       EOP_MOV_IMM(11, 0, 0);                  // mov r11, #0
+       return tcache_ptr - start_ptr;
 }
 
-static void emit_block_epilogue(int icount)
+static int emit_call(int cond, void *target)
 {
-       if (icount > 0xff) { printf("large icount: %i\n", icount); icount = 0xff; }
-       emit_call(regfile_store);
-       EOP_ADD_IMM(0,11,0,icount);             // add r0, r11, #icount
-       EOP_LDMFD_ST(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M); // ldmfd r13!, {r4-r11,lr}
-       EOP_BX(14);                             // bx r14
+       return emit_xbranch(cond, target, 1);
 }
 
-static void emit_pc_dump(int pc)
+static int emit_jump(int cond, void *target)
 {
-       emit_mov_const(A_COND_AL, 3, pc<<16);
-       EOP_STR_IMM(3,7,0x400+6*4);             // str r3, [r7, #(0x400+6*8)]
+       return emit_xbranch(cond, target, 0);
 }
 
-static void handle_caches()
+static void handle_caches(void)
 {
 #ifdef ARM
-       extern void flush_inval_caches(const void *start_addr, const void *end_addr);
-       flush_inval_caches(tcache, tcache_ptr);
+       extern void cache_flush_d_inval_i(const void *start_addr, const void *end_addr);
+       cache_flush_d_inval_i(tcache, tcache_ptr);
 #endif
 }