static int running = 0;
static int last_iram = 0;
#endif
-#ifdef EMBED_INTERPRETER
-static int iram_dirty = 0;
-#endif
// -----------------------------------------------------
// register i/o handlers
return inc;
}
-#define overwite_write(dst, d) \
+#define overwrite_write(dst, d) \
{ \
if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
reg, CADDR, d, inc, (mode>>10)&1);
if (mode & 0x0400) {
- overwite_write(dram[addr], d);
+ overwrite_write(dram[addr], d);
} else dram[addr] = d;
ssp->pmac_write[reg] += inc;
}
elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
if (mode & 0x0400) {
- overwite_write(dram[addr], d);
+ overwrite_write(dram[addr], d);
} else dram[addr] = d;
ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
}
((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
ssp->pmac_write[reg] += inc;
#ifdef EMBED_INTERPRETER
- iram_dirty = 1;
+ ssp->drc.iram_dirty = 1;
#endif
}
else
// 15
static u32 read_AL(void)
{
- if (*(PC-1) == 0x000f) {
+ if (*(PC-1) == 0x000f)
elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
- ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
- }
+ ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
return rAL;
}