// basic, incomplete SSP160x (SSP1601?) interpreter
+// with SVP memory controller emu
+
+// (c) Copyright 2008, Grazvydas "notaz" Ignotas
+// Free for non-commercial use.
+
+// For commercial use, separate licencing terms must be obtained.
+
+
+#include "../../PicoInt.h"
/*
* Register info
- * most names taken from MAME code
*
* 0. "-"
* size: 16
*
* 1. "X"
* size: 16
- * desc: Generic register. When set, updates P (P = X * Y * 2) ??
+ * desc: Generic register. When set, updates P (P = X * Y * 2)
*
* 2. "Y"
* size: 16
- * desc: Generic register. When set, updates P (P = X * Y * 2) ??
+ * desc: Generic register. When set, updates P (P = X * Y * 2)
*
* 3. "A"
* size: 32
*
* 7. "P"
* size: 32
- * desc: multiply result register. Updated after mp* instructions,
- * or writes to X or Y (P = X * Y * 2) ??
+ * desc: multiply result register. P = X * Y * 2
* probably affected by MACS bit in ST.
*
* 8. "PM0" (PM from PMAR name from Tasco's docs)
* Reading the register also shifts it's state (from "waiting for
* address" to "waiting for mode" and back). Reads always return
* address related to last PMx register accressed.
+ * (note: addresses do not wrap).
*
* 15. "AL"
* size: 16
- * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
+ * desc: Accumulator Low. 16 least significant bits of accumulator.
* (normally reading acc (ld X, A) you get 16 most significant bits).
*
*
* 30fe06 - also sync related.
* 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
*
- * TODO:
* + figure out if 'op A, P' is 32bit (nearly sure it is)
- * * what exactly is AL?
* * does mld, mpya load their operands into X and Y?
* * OP simm
*
- * misc:
- * pressing all buttons while resetting game will kick into test mode
- *
* Assumptions in this code
* P is not directly writeable
* flags correspond to full 32bit accumulator
* only Z and N status flags are emulated (others unused by SVP)
* modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
- * modifiers '+' and '+!' act the same (this is most likely wrong)
- * 'ld d, (a)' loads from program ROM
*/
#include "../../PicoInt.h"
#define rXST ssp->gr[SSP_XST].h
#define rPM4 ssp->gr[SSP_PM4].h // 12
// 13
-#define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
+#define rPMC ssp->gr[SSP_PMC] // will keep addr in .l, mode in .h
#define rAL ssp->gr[SSP_A].l
#define rA32 ssp->gr[SSP_A].v
#define IJind (((op>>6)&4)|(op&3))
+#ifndef EMBED_INTERPRETER
#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
+#endif
#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
#define REG_WRITE(r,d) { \
case 0x00: cond = 1; break; /* always true */ \
case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
- default:elprintf(EL_SVP, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
+ default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
}
// ops with accumulator.
#define OP_CHECK32(OP) \
if ((op & 0x0f) == SSP_P) { /* A <- P */ \
read_P(); /* update P */ \
- OP(ssp->gr[SSP_P].v); \
+ OP(rP.v); \
break; \
}
static int running = 0;
static int last_iram = 0;
#endif
+#ifdef EMBED_INTERPRETER
+static int iram_dirty = 0;
+#endif
// -----------------------------------------------------
// register i/o handlers
static void write_ST(u32 d)
{
//if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
- if ((rST ^ d) & 0x0f98) elprintf(EL_SVP, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
+ if ((rST ^ d) & 0x0f98) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
rST = d;
}
int inc = (mode >> 11) & 7;
if (inc != 0) {
if (inc != 7) inc--;
- inc = (1<<16) << inc; // 0 1 2 4 8 16 32 128
+ inc = 1 << inc; // 0 1 2 4 8 16 32 128
if (mode & 0x8000) inc = -inc; // decrement mode
}
return inc;
elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
ssp->emu_status &= ~SSP_PMC_SET;
- if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
+ if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) {
elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
#ifdef USE_DEBUGGER
last_iram = (ssp->RAM1[0]-1)<<1;
+#endif
+#ifdef EMBED_INTERPRETER
+ iram_dirty = 1;
#endif
}
return 0;
unsigned short *dram = (unsigned short *)svp->dram;
if (write)
{
- int mode = ssp->pmac_write[reg]&0xffff;
- int addr = ssp->pmac_write[reg]>>16;
+ int mode = ssp->pmac_write[reg]>>16;
+ int addr = ssp->pmac_write[reg]&0xffff;
if ((mode & 0xb800) == 0xb800)
- elprintf(EL_SVP, "ssp FIXME: mode %04x", mode);
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
if ((mode & 0x43ff) == 0x0018) // DRAM
{
int inc = get_inc(mode);
elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
- reg, CADDR, d, inc >> 16, (mode>>10)&1);
+ reg, CADDR, d, inc, (mode>>10)&1);
if (mode & 0x0400) {
overwite_write(dram[addr], d);
} else dram[addr] = d;
if (mode & 0x0400) {
overwite_write(dram[addr], d);
} else dram[addr] = d;
- ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
+ ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
}
else if ((mode & 0x47ff) == 0x001c) // IRAM
{
int inc = get_inc(mode);
if ((addr&0xfc00) != 0x8000)
elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
- elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc >> 16);
+ elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
ssp->pmac_write[reg] += inc;
}
}
else
{
- int mode = ssp->pmac_read[reg]&0xffff;
- int addr = ssp->pmac_read[reg]>>16;
+ int mode = ssp->pmac_read[reg]>>16;
+ int addr = ssp->pmac_read[reg]&0xffff;
if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
{
elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
- ssp->pmac_read[reg] += 1<<16;
+ ssp->pmac_read[reg] += 1;
d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
}
else if ((mode & 0x47ff) == 0x0018) // DRAM
{
int inc = get_inc(mode);
- elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr], inc >> 16);
+ elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr]);
d = dram[addr];
ssp->pmac_read[reg] += inc;
}
if (d != (u32)-1) return d;
elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
d = rPM0;
+#ifndef EMBED_INTERPRETER
if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
}
+#endif
rPM0 &= ~2; // ?
return d;
}
u32 d = pm_io(1, 0, 0);
if (d != (u32)-1) return d;
// can be removed?
- elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
return rPM1;
}
u32 r = pm_io(1, 1, d);
if (r != (u32)-1) return;
// can be removed?
- elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
rPM1 = d;
}
u32 d = pm_io(2, 0, 0);
if (d != (u32)-1) return d;
// can be removed?
- elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
return rPM2;
}
u32 r = pm_io(2, 1, d);
if (r != (u32)-1) return;
// can be removed?
- elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
rPM2 = d;
}
static u32 read_PM4(void)
{
u32 d = pm_io(4, 0, 0);
+#ifndef EMBED_INTERPRETER
if (d == 0) {
switch (GET_PPC_OFFS()) {
case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
}
}
+#endif
if (d != (u32)-1) return d;
// can be removed?
- elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
return rPM4;
}
u32 r = pm_io(4, 1, d);
if (r != (u32)-1) return;
// can be removed?
- elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
rPM4 = d;
}
// 14
static u32 read_PMC(void)
{
- elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.h,
+ elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.l,
(ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
//if (ssp->emu_status & SSP_PMC_SET)
// elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
ssp->emu_status |= SSP_PMC_SET;
ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
+ return ((rPMC.l << 4) & 0xfff0) | ((rPMC.l >> 4) & 0xf);
} else {
ssp->emu_status |= SSP_PMC_HAVE_ADDR;
+ return rPMC.l;
}
- return rPMC.h;
}
static void write_PMC(u32 d)
// elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
ssp->emu_status |= SSP_PMC_SET;
ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
- rPMC.l = d;
- elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
+ rPMC.h = d;
+ elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.h, GET_PPC_OFFS());
} else {
ssp->emu_status |= SSP_PMC_HAVE_ADDR;
- rPMC.h = d;
- elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
+ rPMC.l = d;
+ elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.l, GET_PPC_OFFS());
}
}
static u32 read_AL(void)
{
if (*(PC-1) == 0x000f) {
- elprintf(EL_SVP|EL_ANOMALY, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
+ elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
}
return rAL;
// -----------------------------------------------------
-void ssp1601_reset(ssp1601_t *l_ssp)
+#if defined(USE_DEBUGGER) //|| defined(EMBED_INTERPRETER)
+static void debug_dump2file(const char *fname, void *mem, int len)
{
- ssp = l_ssp;
- ssp->emu_status = 0;
- ssp->gr[SSP_GR0].v = 0xffff0000;
- rPC = 0x400;
- rSTACK = 0; // ? using ascending stack
- rST = 0;
+ FILE *f = fopen(fname, "wb");
+ unsigned short *p = mem;
+ int i;
+ if (f) {
+ for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
+ fwrite(mem, 1, len, f);
+ fclose(f);
+ for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
+ printf("dumped to %s\n", fname);
+ }
+ else
+ printf("dump failed\n");
}
-
+#endif
#ifdef USE_DEBUGGER
static void debug_dump(void)
{
printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
- printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
+ printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, rP.v);
printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
- printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
+ printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, rPMC.v);
printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
}
}
-static void debug_dump2file(const char *fname, void *mem, int len)
-{
- FILE *f = fopen(fname, "wb");
- unsigned short *p = mem;
- int i;
- if (f) {
- for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
- fwrite(mem, 1, len, f);
- fclose(f);
- for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
- printf("dumped to %s\n", fname);
- }
- else
- printf("dump failed\n");
-}
-
static int bpts[10] = { 0, };
static void debug(unsigned int pc, unsigned int op)
#endif // USE_DEBUGGER
+#ifdef EMBED_INTERPRETER
+static
+#endif
+void ssp1601_reset(ssp1601_t *l_ssp)
+{
+ ssp = l_ssp;
+ ssp->emu_status = 0;
+ ssp->gr[SSP_GR0].v = 0xffff0000;
+ rPC = 0x400;
+ rSTACK = 0; // ? using ascending stack
+ rST = 0;
+}
+
+
+#ifdef EMBED_INTERPRETER
+static
+#endif
void ssp1601_run(int cycles)
{
+#ifndef EMBED_INTERPRETER
SET_PC(rPC);
+#endif
g_cycles = cycles;
while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
// not sure. MAME claims that only hi word is transfered.
read_P(); // update P
- rA32 = ssp->gr[SSP_P].v;
+ rA32 = rP.v;
}
else
{
case 3: rA32 <<= 1; break; // shl
case 6: rA32 = -(signed int)rA32; break; // neg
case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
- default: elprintf(EL_SVP, "ssp FIXME: unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
+ default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
+ op&7, GET_PPC_OFFS());
}
UPD_ACC_ZN // ?
}
break;
}
- // ???
+ // mpys?
case 0x1b:
-#if 0
- // very uncertain about this one. What about b?
- if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
read_P(); // update P
- rA32 -= ssp->gr[SSP_P].v; // maybe only upper word?
- // UPD_ACC_ZN // I've seen code checking flags after this
+ rA32 -= rP.v; // maybe only upper word?
+ UPD_ACC_ZN // there checking flags after this
rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
-#endif
break;
// mpya (rj), (ri), b
case 0x4b:
- // dunno if this is correct. What about b?
- if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
read_P(); // update P
- rA32 += ssp->gr[SSP_P].v; // confirmed to be 32bit
+ rA32 += rP.v; // confirmed to be 32bit
UPD_ACC_ZN // ?
rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
// mld (rj), (ri), b
case 0x5b:
- // dunno if this is correct. What about b?
- if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
rA32 = 0;
rST &= 0x0fff; // ?
rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
// OP simm
- case 0x1c: OP_SUBA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
- case 0x3c: OP_CMPA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
- case 0x4c: OP_ADDA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
+ case 0x1c: OP_SUBA(op & 0xff); break;
+ case 0x3c: OP_CMPA(op & 0xff); break;
+ case 0x4c: OP_ADDA(op & 0xff); break;
// MAME code only does LSB of top word, but this looks wrong to me.
- case 0x5c: OP_ANDA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
- case 0x6c: OP_ORA (op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
- case 0x7c: OP_EORA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
+ case 0x5c: OP_ANDA(op & 0xff); break;
+ case 0x6c: OP_ORA (op & 0xff); break;
+ case 0x7c: OP_EORA(op & 0xff); break;
+#ifdef EMBED_INTERPRETER
+ case 0x7f: goto interp_end; /* pseudo op */
+#endif
default:
elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
break;
g_cycles--;
}
- read_P(); // update P
rPC = GET_PC();
+#ifdef EMBED_INTERPRETER
+interp_end:
+#endif
+ read_P(); // update P
if (ssp->gr[SSP_GR0].v != 0xffff0000)
elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
notaz.gp2x.de / picodrive.git / blobdiff