// basic, incomplete SSP160x (SSP1601?) interpreter
+// with SVP memory controller emu
+
+// (c) Copyright 2008, Grazvydas "notaz" Ignotas
+// Free for non-commercial use.
+
+// For commercial use, separate licencing terms must be obtained.
+
+
+#include "../../PicoInt.h"
/*
* Register info
- * most names taken from MAME code
*
* 0. "-"
* size: 16
*
* 1. "X"
* size: 16
- * desc: Generic register. When set, updates P (P = X * Y * 2) ??
+ * desc: Generic register. When set, updates P (P = X * Y * 2)
*
* 2. "Y"
* size: 16
- * desc: Generic register. When set, updates P (P = X * Y * 2) ??
+ * desc: Generic register. When set, updates P (P = X * Y * 2)
*
* 3. "A"
* size: 32
*
* 7. "P"
* size: 32
- * desc: multiply result register. Updated after mp* instructions,
- * or writes to X or Y (P = X * Y * 2) ??
+ * desc: multiply result register. P = X * Y * 2
* probably affected by MACS bit in ST.
*
* 8. "PM0" (PM from PMAR name from Tasco's docs)
* size: 16?
* desc: Programmable Memory access register.
* On reset, or when one (both?) GP0 bits are clear,
- * acts as some additional status reg?
+ * acts as status for XST, mapped at 015004 at 68k side:
+ * bit0: ssp has written something to XST (cleared when 015004 is read)
+ * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
*
* 9. "PM1"
* size: 16?
*
* 11. "XST"
* size: 16?
- * desc: eXternal STate. Mapped to a15000 at 68k side.
+ * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
* Can be programmed as PMAR? (only seen in test mode code)
+ * Affects PM0 when written to?
*
* 12. "PM4"
* size: 16?
* size: 32?
* desc: Programmable Memory access Control. Set using 2 16bit writes,
* first address, then mode word. After setting PMAC, PMAR sould
- * be accessed to program it.
+ * be blind accessed (ld -, PMx or ld PMx, -) to program it for
+ * reading and writing respectively.
+ * Reading the register also shifts it's state (from "waiting for
+ * address" to "waiting for mode" and back). Reads always return
+ * address related to last PMx register accressed.
+ * (note: addresses do not wrap).
*
* 15. "AL"
* size: 16
- * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
+ * desc: Accumulator Low. 16 least significant bits of accumulator.
* (normally reading acc (ld X, A) you get 16 most significant bits).
*
*
*
* Instruction notes
*
+ * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
+ *
* mld (rj), (ri) [, b]
* operation: A = 0; P = (rj) * (ri)
* notes: based on IIR_4B.SC sample. flags? what is b???
- * TODO: figure out if (rj) and (ri) get loaded in X and Y
*
* mpya (rj), (ri) [, b]
* name: multiply and add?
* name: multiply and subtract?
* notes: not used by VR code.
*
+ * mod cond, op
+ * mod cond, shr does arithmetic shift
+ *
+ * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
+ *
+ * memory map:
+ * 000000 - 1fffff ROM, accessable by both
+ * 200000 - 2fffff unused?
+ * 300000 - 31ffff DRAM, both
+ * 320000 - 38ffff unused?
+ * 390000 - 3907ff IRAM. can only be accessed by ssp?
+ * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
+ * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
+ *
+ * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
+ * 30fe06 - also sync related.
+ * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
+ *
+ * + figure out if 'op A, P' is 32bit (nearly sure it is)
+ * * does mld, mpya load their operands into X and Y?
+ * * OP simm
*
* Assumptions in this code
* P is not directly writeable
* flags correspond to full 32bit accumulator
* only Z and N status flags are emulated (others unused by SVP)
* modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
- * modifiers '+' and '+!' act the same (this is most likely wrong)
- * 'ld d, (a)' loads from program ROM
*/
#include "../../PicoInt.h"
#define u32 unsigned int
+//#define USE_DEBUGGER
+
// 0
#define rX ssp->gr[SSP_X].h
#define rY ssp->gr[SSP_Y].h
#define rXST ssp->gr[SSP_XST].h
#define rPM4 ssp->gr[SSP_PM4].h // 12
// 13
-#define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
+#define rPMC ssp->gr[SSP_PMC] // will keep addr in .l, mode in .h
#define rAL ssp->gr[SSP_A].l
#define rA32 ssp->gr[SSP_A].v
#define IJind (((op>>6)&4)|(op&3))
+#ifndef EMBED_INTERPRETER
#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
+#endif
#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
-// if r is 'A', should we set flags?
#define REG_WRITE(r,d) { \
int r1 = r; \
if (r1 >= 4) write_handlers[r1](d); \
}
// flags
-#define FLAG_L (1<<0xc)
-#define FLAG_Z (1<<0xd)
-#define FLAG_V (1<<0xe)
-#define FLAG_N (1<<0xf)
+#define SSP_FLAG_L (1<<0xc)
+#define SSP_FLAG_Z (1<<0xd)
+#define SSP_FLAG_V (1<<0xe)
+#define SSP_FLAG_N (1<<0xf)
// update ZN according to 32bit ACC.
#define UPD_ACC_ZN \
- rST &= ~(FLAG_Z|FLAG_N); \
- if (!rA32) rST |= FLAG_Z; \
- else rST |= (rA32>>16)&FLAG_N;
+ rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
+ if (!rA32) rST |= SSP_FLAG_Z; \
+ else rST |= (rA32>>16)&SSP_FLAG_N;
// it seems SVP code never checks for L and OV, so we leave them out.
-// rST |= (t>>4)&FLAG_L;
-#define UPD_t_LZVN \
- rST &= ~(FLAG_L|FLAG_Z|FLAG_V|FLAG_N); \
- if (!t) rST |= FLAG_Z; \
- else rST |= t&FLAG_N; \
+// rST |= (t>>4)&SSP_FLAG_L;
+#define UPD_LZVN \
+ rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
+ if (!rA32) rST |= SSP_FLAG_Z; \
+ else rST |= (rA32>>16)&SSP_FLAG_N;
// standard cond processing.
// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
#define COND_CHECK \
switch (op&0xf0) { \
case 0x00: cond = 1; break; /* always true */ \
- case 0x50: cond = !((rST ^ (op<<5)) & FLAG_Z); break; /* Z matches f(?) bit */ \
- case 0x70: cond = !((rST ^ (op<<7)) & FLAG_N); break; /* N matches f(?) bit */ \
- default:elprintf(EL_SVP, "unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
+ case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
+ case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
+ default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
}
// ops with accumulator.
// how is low word really affected by these?
-// not sure if 'ld A' affects flags (assume it does..)
+// nearly sure 'ld A' doesn't affect flags
#define OP_LDA(x) \
- ssp->gr[SSP_A].h = x; \
- UPD_ACC_ZN
+ ssp->gr[SSP_A].h = x
+
+#define OP_LDA32(x) \
+ rA32 = x
#define OP_SUBA(x) { \
- u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
- UPD_t_LZVN \
- ssp->gr[SSP_A].h = t; \
+ rA32 -= (x) << 16; \
+ UPD_LZVN \
+}
+
+#define OP_SUBA32(x) { \
+ rA32 -= (x); \
+ UPD_LZVN \
}
#define OP_CMPA(x) { \
- u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
- UPD_t_LZVN \
+ u32 t = rA32 - ((x) << 16); \
+ rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
+ if (!t) rST |= SSP_FLAG_Z; \
+ else rST |= (t>>16)&SSP_FLAG_N; \
+}
+
+#define OP_CMPA32(x) { \
+ u32 t = rA32 - (x); \
+ rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
+ if (!t) rST |= SSP_FLAG_Z; \
+ else rST |= (t>>16)&SSP_FLAG_N; \
}
#define OP_ADDA(x) { \
- u32 t = (ssp->gr[SSP_A].v >> 16) + (x); \
- UPD_t_LZVN \
- ssp->gr[SSP_A].h = t; \
+ rA32 += (x) << 16; \
+ UPD_LZVN \
+}
+
+#define OP_ADDA32(x) { \
+ rA32 += (x); \
+ UPD_LZVN \
}
#define OP_ANDA(x) \
- ssp->gr[SSP_A].v &= (x) << 16; \
+ rA32 &= (x) << 16; \
+ UPD_ACC_ZN
+
+#define OP_ANDA32(x) \
+ rA32 &= (x); \
UPD_ACC_ZN
#define OP_ORA(x) \
- ssp->gr[SSP_A].v |= (x) << 16; \
+ rA32 |= (x) << 16; \
+ UPD_ACC_ZN
+
+#define OP_ORA32(x) \
+ rA32 |= (x); \
UPD_ACC_ZN
#define OP_EORA(x) \
- ssp->gr[SSP_A].v ^= (x) << 16; \
+ rA32 ^= (x) << 16; \
+ UPD_ACC_ZN
+
+#define OP_EORA32(x) \
+ rA32 ^= (x); \
UPD_ACC_ZN
+#define OP_CHECK32(OP) \
+ if ((op & 0x0f) == SSP_P) { /* A <- P */ \
+ read_P(); /* update P */ \
+ OP(rP.v); \
+ break; \
+}
+
+
static ssp1601_t *ssp = NULL;
static unsigned short *PC;
static int g_cycles;
-// debug
+
+#ifdef USE_DEBUGGER
static int running = 0;
+static int last_iram = 0;
+#endif
+#ifdef EMBED_INTERPRETER
+static int iram_dirty = 0;
+#endif
// -----------------------------------------------------
// register i/o handlers
// 0-4, 13
static u32 read_unknown(void)
{
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: unknown read @ %04x", GET_PPC_OFFS());
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
return 0;
}
static void write_unknown(u32 d)
{
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: unknown write @ %04x", GET_PPC_OFFS());
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
}
// 4
static void write_ST(u32 d)
{
- if ((rST ^ d) & 7) {
- elprintf(EL_SVP, "ssp16: RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
- running = 0;
- }
+ //if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
+ if ((rST ^ d) & 0x0f98) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
rST = d;
}
// 5
static u32 read_STACK(void)
{
- //elprintf(EL_SVP, "pop %i @ %04x", rSTACK, GET_PPC_OFFS());
--rSTACK;
if ((short)rSTACK < 0) {
rSTACK = 5;
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
}
return ssp->stack[rSTACK];
}
static void write_STACK(u32 d)
{
if (rSTACK >= 6) {
- //running = 0;
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
rSTACK = 0;
}
ssp->stack[rSTACK++] = d;
// 7
static u32 read_P(void)
{
- rP.v = (u32)rX * rY * 2;
+ int m1 = (signed short)rX;
+ int m2 = (signed short)rY;
+ rP.v = (m1 * m2 * 2);
return rP.h;
}
// -----------------------------------------------------
-static void iram_write(int addr, u32 d, int reg, int inc)
+static int get_inc(int mode)
{
- if ((addr&0xfc00) != 0x8000)
- elprintf(EL_SVP|EL_ANOMALY, "ssp invalid IRAM addr: %04x", addr<<1);
- elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
- ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
- ssp->pmac_write[reg] += inc<<16;
+ int inc = (mode >> 11) & 7;
+ if (inc != 0) {
+ if (inc != 7) inc--;
+ inc = 1 << inc; // 0 1 2 4 8 16 32 128
+ if (mode & 0x8000) inc = -inc; // decrement mode
+ }
+ return inc;
+}
+
+#define overwite_write(dst, d) \
+{ \
+ if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
+ if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
+ if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
+ if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
}
static u32 pm_io(int reg, int write, u32 d)
{
- if (ssp->emu_status & SSP_PMC_SET) {
+ if (ssp->emu_status & SSP_PMC_SET)
+ {
+ // this MUST be blind r or w
+ if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
+ reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
+ ssp->emu_status &= ~SSP_PMC_SET;
+ return 0;
+ }
elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
ssp->emu_status &= ~SSP_PMC_SET;
+ if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) {
+ elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
+#ifdef USE_DEBUGGER
+ last_iram = (ssp->RAM1[0]-1)<<1;
+#endif
+#ifdef EMBED_INTERPRETER
+ iram_dirty = 1;
+#endif
+ }
return 0;
}
// just in case
- ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
+ if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
+ reg, write ? 'w' : 'r', GET_PPC_OFFS());
+ ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
+ }
-// if (ssp->pmac_read[reg] != 0)
if (reg == 4 || (rST & 0x60))
{
+ #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
+ unsigned short *dram = (unsigned short *)svp->dram;
if (write)
{
- int mode = ssp->pmac_write[reg]&0xffff;
- int addr = ssp->pmac_write[reg]>>16;
- switch (mode) {
- case 0x0018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x", addr<<1, d);
- ((unsigned short *)svp->dram)[addr] = d;
- break;
- case 0x0818: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (inc 1)", addr<<1, d);
- ((unsigned short *)svp->dram)[addr] = d;
- ssp->pmac_write[reg] += 1<<16;
- break;
- case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
- case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
- default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
- reg, mode, addr<<1, d, GET_PPC_OFFS()); break;
+ int mode = ssp->pmac_write[reg]>>16;
+ int addr = ssp->pmac_write[reg]&0xffff;
+ if ((mode & 0xb800) == 0xb800)
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
+ if ((mode & 0x43ff) == 0x0018) // DRAM
+ {
+ int inc = get_inc(mode);
+ elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
+ reg, CADDR, d, inc, (mode>>10)&1);
+ if (mode & 0x0400) {
+ overwite_write(dram[addr], d);
+ } else dram[addr] = d;
+ ssp->pmac_write[reg] += inc;
+ }
+ else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
+ {
+ elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
+ reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
+ if (mode & 0x0400) {
+ overwite_write(dram[addr], d);
+ } else dram[addr] = d;
+ ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
+ }
+ else if ((mode & 0x47ff) == 0x001c) // IRAM
+ {
+ int inc = get_inc(mode);
+ if ((addr&0xfc00) != 0x8000)
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
+ elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
+ ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
+ ssp->pmac_write[reg] += inc;
+ }
+ else
+ {
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
+ reg, mode, CADDR, d, GET_PPC_OFFS());
}
}
else
{
- int mode = ssp->pmac_read[reg]&0xffff;
- int addr = ssp->pmac_read[reg]>>16;
- switch (mode) {
- case 0x0809: elprintf(EL_SVP, "ssp ROM r [%06x] %04x", (addr|((mode&0xf)<<16))<<1,
- ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
- // possibly correct, the first word read is some sort of counter, sane values in ROM
- ssp->pmac_read[reg] += 1<<16;
- return ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
- case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", addr<<1, ((unsigned short *)svp->dram)[addr]);
- return ((unsigned short *)svp->dram)[addr]; // checked
- case 0x0818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 1)", addr<<1, ((unsigned short *)svp->dram)[addr]);
- ssp->pmac_read[reg] += 1<<16;
- return ((unsigned short *)svp->dram)[addr];
- case 0x3018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 32)", addr<<1, ((unsigned short *)svp->dram)[addr]);
- ssp->pmac_read[reg] += 32<<16;
- return ((unsigned short *)svp->dram)[addr];
- default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled read mode %04x, [%06x] @ %04x",
- reg, mode, addr<<1, GET_PPC_OFFS()); break;
+ int mode = ssp->pmac_read[reg]>>16;
+ int addr = ssp->pmac_read[reg]&0xffff;
+ if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
+ {
+ elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
+ ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
+ ssp->pmac_read[reg] += 1;
+ d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
+ }
+ else if ((mode & 0x47ff) == 0x0018) // DRAM
+ {
+ int inc = get_inc(mode);
+ elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr]);
+ d = dram[addr];
+ ssp->pmac_read[reg] += inc;
+ }
+ else
+ {
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
+ reg, mode, CADDR, GET_PPC_OFFS());
+ d = 0;
}
}
- return 0;
+
+ // PMC value corresponds to last PMR accessed (not sure).
+ rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
+
+ return d;
}
return (u32)-1;
{
u32 d = pm_io(0, 0, 0);
if (d != (u32)-1) return d;
- if (GET_PPC_OFFS() != 0x800 || rPM0 != 0) // debug
- elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
- return rPM0;
+ elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
+ d = rPM0;
+#ifndef EMBED_INTERPRETER
+ if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
+ ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
+ }
+#endif
+ rPM0 &= ~2; // ?
+ return d;
}
static void write_PM0(u32 d)
u32 d = pm_io(1, 0, 0);
if (d != (u32)-1) return d;
// can be removed?
- elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
return rPM1;
}
u32 r = pm_io(1, 1, d);
if (r != (u32)-1) return;
// can be removed?
- elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
rPM1 = d;
}
u32 d = pm_io(2, 0, 0);
if (d != (u32)-1) return d;
// can be removed?
- elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
return rPM2;
}
u32 r = pm_io(2, 1, d);
if (r != (u32)-1) return;
// can be removed?
- elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
rPM2 = d;
}
if (r != (u32)-1) return;
elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
+ rPM0 |= 1;
rXST = d;
}
static u32 read_PM4(void)
{
u32 d = pm_io(4, 0, 0);
+#ifndef EMBED_INTERPRETER
+ if (d == 0) {
+ switch (GET_PPC_OFFS()) {
+ case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
+ case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
+ }
+ }
+#endif
if (d != (u32)-1) return d;
// can be removed?
- elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
return rPM4;
}
u32 r = pm_io(4, 1, d);
if (r != (u32)-1) return;
// can be removed?
- elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
rPM4 = d;
}
// 14
static u32 read_PMC(void)
{
+ elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.l,
+ (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
- if (ssp->emu_status & SSP_PMC_SET)
- elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
+ //if (ssp->emu_status & SSP_PMC_SET)
+ // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
ssp->emu_status |= SSP_PMC_SET;
ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
- return rPMC.l;
+ return ((rPMC.l << 4) & 0xfff0) | ((rPMC.l >> 4) & 0xf);
} else {
ssp->emu_status |= SSP_PMC_HAVE_ADDR;
- return rPMC.h;
+ return rPMC.l;
}
}
static void write_PMC(u32 d)
{
if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
- if (ssp->emu_status & SSP_PMC_SET)
- elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
+ //if (ssp->emu_status & SSP_PMC_SET)
+ // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
ssp->emu_status |= SSP_PMC_SET;
ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
- rPMC.l = d;
+ rPMC.h = d;
+ elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.h, GET_PPC_OFFS());
} else {
ssp->emu_status |= SSP_PMC_HAVE_ADDR;
- rPMC.h = d;
+ rPMC.l = d;
+ elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.l, GET_PPC_OFFS());
}
}
// 15
static u32 read_AL(void)
{
- // TODO: figure out what's up with those blind reads..
+ if (*(PC-1) == 0x000f) {
+ elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
+ ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
+ }
return rAL;
}
static u32 ptr1_read_(int ri, int isj2, int modi3)
{
//int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
- int t = ri | isj2 | modi3;
+ u32 mask, add = 0, t = ri | isj2 | modi3;
+ unsigned char *rp = NULL;
switch (t)
{
// mod=0 (00)
case 0x06: return ssp->RAM1[ssp->r1[t&3]];
case 0x07: return ssp->RAM1[0];
// mod=1 (01), "+!"
- // mod=3, "+"
case 0x08:
- case 0x18:
case 0x09:
- case 0x19:
- case 0x0a:
- case 0x1a: return ssp->RAM0[ssp->r0[t&3]++];
+ case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
case 0x0b: return ssp->RAM0[1];
case 0x0c:
- case 0x1c:
case 0x0d:
- case 0x1d:
- case 0x0e:
- case 0x1e: return ssp->RAM1[ssp->r1[t&3]++];
+ case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
case 0x0f: return ssp->RAM1[1];
// mod=2 (10), "-"
case 0x10:
case 0x11:
- case 0x12: return ssp->RAM0[ssp->r0[t&3]--];
+ case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
+ if (!(rST&7)) { (*rp)--; return t; }
+ add = -1; goto modulo;
case 0x13: return ssp->RAM0[2];
case 0x14:
case 0x15:
- case 0x16: return ssp->RAM1[ssp->r1[t&3]--];
+ case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
+ if (!(rST&7)) { (*rp)--; return t; }
+ add = -1; goto modulo;
case 0x17: return ssp->RAM1[2];
- // mod=3 (11)
+ // mod=3 (11), "+"
+ case 0x18:
+ case 0x19:
+ case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
+ if (!(rST&7)) { (*rp)++; return t; }
+ add = 1; goto modulo;
case 0x1b: return ssp->RAM0[3];
+ case 0x1c:
+ case 0x1d:
+ case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
+ if (!(rST&7)) { (*rp)++; return t; }
+ add = 1; goto modulo;
case 0x1f: return ssp->RAM1[3];
}
return 0;
+
+modulo:
+ mask = (1 << (rST&7)) - 1;
+ *rp = (*rp & ~mask) | ((*rp + add) & mask);
+ return t;
}
static void ptr1_write(int op, u32 d)
// mod=3 (11)
case 0x1b: mv = ssp->RAM0[3]++; break;
case 0x1f: mv = ssp->RAM1[3]++; break;
- default: elprintf(EL_SVP|EL_ANOMALY, "invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
+ default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
return 0;
}
// -----------------------------------------------------
-void ssp1601_reset(ssp1601_t *l_ssp)
+#if defined(USE_DEBUGGER) //|| defined(EMBED_INTERPRETER)
+static void debug_dump2file(const char *fname, void *mem, int len)
{
- ssp = l_ssp;
- ssp->emu_status = 0;
- ssp->gr[SSP_GR0].v = 0xffff0000;
- rPC = 0x400;
- rSTACK = 0; // ? using ascending stack
+ FILE *f = fopen(fname, "wb");
+ unsigned short *p = mem;
+ int i;
+ if (f) {
+ for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
+ fwrite(mem, 1, len, f);
+ fclose(f);
+ for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
+ printf("dumped to %s\n", fname);
+ }
+ else
+ printf("dump failed\n");
}
+#endif
-
+#ifdef USE_DEBUGGER
static void debug_dump(void)
{
printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
- printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
+ printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, rP.v);
printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
- printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
- printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&FLAG_N?'N':'n', rST&FLAG_V?'V':'v',
- rST&FLAG_Z?'Z':'z', rST&FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
+ printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, rPMC.v);
+ printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
+ rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
break;
}
- case 'd': {
- FILE *f = fopen("dump.bin", "wb");
- unsigned short *p = (unsigned short *)svp->iram_rom;
- int i;
- if (f) {
- for (i = 0; i < 0x10000; i++) p[i] = (p[i]<<8) | (p[i]>>8);
- fwrite(svp->iram_rom, 1, 0x20000, f);
- fclose(f);
- for (i = 0; i < 0x10000; i++) p[i] = (p[i]<<8) | (p[i]>>8);
- printf("dumped to dump.bin\n");
- }
- else
- printf("dump failed\n");
+ case 'd':
+ sprintf(buff, "iramrom_%04x.bin", last_iram);
+ debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
+ debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
break;
- }
default: printf("unknown command\n"); break;
}
}
}
+#endif // USE_DEBUGGER
+
+#ifdef EMBED_INTERPRETER
+static
+#endif
+void ssp1601_reset(ssp1601_t *l_ssp)
+{
+ ssp = l_ssp;
+ ssp->emu_status = 0;
+ ssp->gr[SSP_GR0].v = 0xffff0000;
+ rPC = 0x400;
+ rSTACK = 0; // ? using ascending stack
+ rST = 0;
+}
+
+
+#ifdef EMBED_INTERPRETER
+static
+#endif
void ssp1601_run(int cycles)
{
+#ifndef EMBED_INTERPRETER
SET_PC(rPC);
+#endif
g_cycles = cycles;
-//running = 0;
- while (g_cycles > 0)
+ while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
{
int op;
u32 tmpv;
op = *PC++;
+#ifdef USE_DEBUGGER
debug(GET_PC()-1, op);
+#endif
switch (op >> 9)
{
// ld d, s
if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
// not sure. MAME claims that only hi word is transfered.
read_P(); // update P
- ssp->gr[SSP_A].v = ssp->gr[SSP_P].v;
+ rA32 = rP.v;
}
else
{
COND_CHECK
if (cond) {
switch (op & 7) {
- case 2: rA32 >>= 1; break; // shr
+ case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
case 3: rA32 <<= 1; break; // shl
- case 6: rA32 = -(int)rA32; break; // neg
- case 7: if ((int)rA32 < 0) rA32 = -(int)rA32; break; // abs
- default: elprintf(EL_SVP, "ssp16: unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
+ case 6: rA32 = -(signed int)rA32; break; // neg
+ case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
+ default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
+ op&7, GET_PPC_OFFS());
}
- UPD_ACC_ZN
+ UPD_ACC_ZN // ?
}
break;
}
+ // mpys?
+ case 0x1b:
+ read_P(); // update P
+ rA32 -= rP.v; // maybe only upper word?
+ UPD_ACC_ZN // there checking flags after this
+ rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
+ rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
+ break;
+
// mpya (rj), (ri), b
case 0x4b:
- // dunno if this is correct. What about b?
read_P(); // update P
- ssp->gr[SSP_A].v += ssp->gr[SSP_P].v; // maybe only upper word?
+ rA32 += rP.v; // confirmed to be 32bit
+ UPD_ACC_ZN // ?
rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
break;
// mld (rj), (ri), b
case 0x5b:
- // dunno if this is correct. What about b?
- ssp->gr[SSP_A].v = 0; // maybe only upper word?
+ rA32 = 0;
+ rST &= 0x0fff; // ?
rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
break;
// OP a, s
- case 0x10: tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
- case 0x30: tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
- case 0x40: tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
- case 0x50: tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
- case 0x60: tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
- case 0x70: tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
+ case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
+ case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
+ case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
+ case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
+ case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
+ case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
// OP a, (ri)
case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
case 0x6c: OP_ORA (op & 0xff); break;
case 0x7c: OP_EORA(op & 0xff); break;
+#ifdef EMBED_INTERPRETER
+ case 0x7f: goto interp_end; /* pseudo op */
+#endif
default:
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: unhandled op %04x @ %04x", op, GET_PPC_OFFS());
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
break;
}
g_cycles--;
}
- read_P(); // update P
rPC = GET_PC();
+#ifdef EMBED_INTERPRETER
+interp_end:
+#endif
+ read_P(); // update P
if (ssp->gr[SSP_GR0].v != 0xffff0000)
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
}
notaz.gp2x.de / picodrive.git / blobdiff