// basic, incomplete SSP160x (SSP1601?) interpreter
+// with SVP memory controller emu
+
+// (c) Copyright 2008, Grazvydas "notaz" Ignotas
+// Free for non-commercial use.
+
+// For commercial use, separate licencing terms must be obtained.
+
+
+//#define USE_DEBUGGER
+/* detect ops with unimplemented/invalid fields.
+ * Useful for homebrew or if a new VR revision pops up. */
+//#define DO_CHECKS
+
+#include "../../PicoInt.h"
/*
* Register info
- * most names taken from MAME code
*
* 0. "-"
* size: 16
*
* 1. "X"
* size: 16
- * desc: Generic register. When set, updates P (P = X * Y * 2) ??
+ * desc: Generic register. When set, updates P (P = X * Y * 2)
*
* 2. "Y"
* size: 16
- * desc: Generic register. When set, updates P (P = X * Y * 2) ??
+ * desc: Generic register. When set, updates P (P = X * Y * 2)
*
* 3. "A"
* size: 32
*
* 7. "P"
* size: 32
- * desc: multiply result register. Updated after mp* instructions,
- * or writes to X or Y (P = X * Y * 2) ??
+ * desc: multiply result register. P = X * Y * 2
* probably affected by MACS bit in ST.
*
* 8. "PM0" (PM from PMAR name from Tasco's docs)
* size: 32?
* desc: Programmable Memory access Control. Set using 2 16bit writes,
* first address, then mode word. After setting PMAC, PMAR sould
- * be accessed to program it.
+ * be blind accessed (ld -, PMx or ld PMx, -) to program it for
+ * reading and writing respectively.
+ * Reading the register also shifts it's state (from "waiting for
+ * address" to "waiting for mode" and back). Reads always return
+ * address related to last PMx register accressed.
+ * (note: addresses do not wrap).
*
* 15. "AL"
* size: 16
- * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
+ * desc: Accumulator Low. 16 least significant bits of accumulator.
* (normally reading acc (ld X, A) you get 16 most significant bits).
*
*
* These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
* ar probably invalid.
*
- * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
+ * r3 and r7 are special and can not be changed (at least Samsung samples and VR code never do).
* They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
* Samsung's old DSP page claims that).
* 1 of these 4 modifiers must be used (short form direct addressing?):
* mld (rj), (ri) [, b]
* operation: A = 0; P = (rj) * (ri)
* notes: based on IIR_4B.SC sample. flags? what is b???
- * TODO: figure out if (rj) and (ri) get loaded in X and Y
*
* mpya (rj), (ri) [, b]
* name: multiply and add?
*
* 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
* 30fe06 - also sync related.
- * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
- *
- * TODO:
- * + figure out if 'op A, P' is 32bit (nearly sure it is)
- * * what exactly is AL?
- * * does mld, mpya load their operands into X and Y?
- * * OP simm
- *
- * misc:
- * pressing all buttons while resetting game will kick into test mode
+ * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by VR.
*
- * Assumptions in this code
- * P is not directly writeable
- * flags correspond to full 32bit accumulator
- * only Z and N status flags are emulated (others unused by SVP)
- * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
- * modifiers '+' and '+!' act the same (this is most likely wrong)
- * 'ld d, (a)' loads from program ROM
+ * Assumptions and limitations in this code
+ * only Z and N status flags are emulated (others unused by VR)
+ * so all condition checks except N and Z are ignored (not used by VR)
+ * modifiers for 'OP a, ri' and ((ri)) are ignored (not used by VR)
+ * loop repeat mode when (ri) is destination is ignored
+ * ops not used by VR are not implemented
*/
#include "../../PicoInt.h"
#define rXST ssp->gr[SSP_XST].h
#define rPM4 ssp->gr[SSP_PM4].h // 12
// 13
-#define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
+#define rPMC ssp->gr[SSP_PMC] // will keep addr in .l, mode in .h
#define rAL ssp->gr[SSP_A].l
#define rA32 ssp->gr[SSP_A].v
if (!rA32) rST |= SSP_FLAG_Z; \
else rST |= (rA32>>16)&SSP_FLAG_N;
-#define UPD_t_LZVN \
- rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
- if (!t) rST |= SSP_FLAG_Z; \
- else rST |= t&SSP_FLAG_N; \
-
// standard cond processing.
-// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
+// again, only Z and N is checked, as VR doesn't seem to use any other conds.
#define COND_CHECK \
switch (op&0xf0) { \
case 0x00: cond = 1; break; /* always true */ \
case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
- default:elprintf(EL_SVP, "unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
+ default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
}
// ops with accumulator.
ssp->gr[SSP_A].h = x
#define OP_LDA32(x) \
- ssp->gr[SSP_A].v = x
+ rA32 = x
#define OP_SUBA(x) { \
- u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
- UPD_t_LZVN \
- ssp->gr[SSP_A].h = t; \
+ rA32 -= (x) << 16; \
+ UPD_LZVN \
}
#define OP_SUBA32(x) { \
- ssp->gr[SSP_A].v -= (x); \
+ rA32 -= (x); \
UPD_LZVN \
}
#define OP_CMPA(x) { \
- u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
- UPD_t_LZVN \
+ u32 t = rA32 - ((x) << 16); \
+ rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
+ if (!t) rST |= SSP_FLAG_Z; \
+ else rST |= (t>>16)&SSP_FLAG_N; \
}
#define OP_CMPA32(x) { \
- u32 t = ssp->gr[SSP_A].v - (x); \
+ u32 t = rA32 - (x); \
rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
if (!t) rST |= SSP_FLAG_Z; \
else rST |= (t>>16)&SSP_FLAG_N; \
}
#define OP_ADDA(x) { \
- u32 t = (ssp->gr[SSP_A].v >> 16) + (x); \
- UPD_t_LZVN \
- ssp->gr[SSP_A].h = t; \
+ rA32 += (x) << 16; \
+ UPD_LZVN \
}
#define OP_ADDA32(x) { \
- ssp->gr[SSP_A].v += (x); \
+ rA32 += (x); \
UPD_LZVN \
}
#define OP_ANDA(x) \
- ssp->gr[SSP_A].v &= (x) << 16; \
+ rA32 &= (x) << 16; \
UPD_ACC_ZN
#define OP_ANDA32(x) \
- ssp->gr[SSP_A].v &= (x); \
+ rA32 &= (x); \
UPD_ACC_ZN
#define OP_ORA(x) \
- ssp->gr[SSP_A].v |= (x) << 16; \
+ rA32 |= (x) << 16; \
UPD_ACC_ZN
#define OP_ORA32(x) \
- ssp->gr[SSP_A].v |= (x); \
+ rA32 |= (x); \
UPD_ACC_ZN
#define OP_EORA(x) \
- ssp->gr[SSP_A].v ^= (x) << 16; \
+ rA32 ^= (x) << 16; \
UPD_ACC_ZN
#define OP_EORA32(x) \
- ssp->gr[SSP_A].v ^= (x); \
+ rA32 ^= (x); \
UPD_ACC_ZN
-#define OP_CHECK32(OP) \
- if ((op & 0x0f) == SSP_P) { /* A <- P */ \
- read_P(); /* update P */ \
- OP(ssp->gr[SSP_P].v); \
- break; \
+#define OP_CHECK32(OP) { \
+ if ((op & 0x0f) == SSP_P) { /* A <- P */ \
+ read_P(); /* update P */ \
+ OP(rP.v); \
+ break; \
+ } \
+ if ((op & 0x0f) == SSP_A) { /* A <- A */ \
+ OP(rA32); \
+ break; \
+ } \
}
-static ssp1601_t *ssp = NULL;
+#ifdef DO_CHECKS
+#define CHECK_IMM16() if (op&0x1ff) elprintf(EL_ANOMALY, "imm bits! %04x @ %04x", op, GET_PPC_OFFS())
+#define CHECK_B_SET() if (op&0x100) elprintf(EL_ANOMALY, "b set! %04x @ %04x", op, GET_PPC_OFFS())
+#define CHECK_B_CLEAR() if (!(op&0x100)) elprintf(EL_ANOMALY, "b clear! %04x @ %04x", op, GET_PPC_OFFS())
+#define CHECK_MOD() if (op&0x00c) elprintf(EL_ANOMALY, "mod bits! %04x @ %04x", op, GET_PPC_OFFS())
+#define CHECK_10f() if (op&0x10f) elprintf(EL_ANOMALY, "bits 10f! %04x @ %04x", op, GET_PPC_OFFS())
+#define CHECK_008() if (op&0x008) elprintf(EL_ANOMALY, "bits 008! %04x @ %04x", op, GET_PPC_OFFS())
+#define CHECK_00f() if (op&0x00f) elprintf(EL_ANOMALY, "bits 00f! %04x @ %04x", op, GET_PPC_OFFS())
+#define CHECK_0f0() if (op&0x0f0) elprintf(EL_ANOMALY, "bits 0f0! %04x @ %04x", op, GET_PPC_OFFS())
+#define CHECK_1f0() if (op&0x1f0) elprintf(EL_ANOMALY, "bits 1f0! %04x @ %04x", op, GET_PPC_OFFS())
+#define CHECK_RPL() if (rST&7) elprintf(EL_ANOMALY, "unhandled RPL! %04x @ %04x", op, GET_PPC_OFFS())
+#define CHECK_ST(d) if((rST^d)&0xf98)elprintf(EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS())
+#else
+#define CHECK_IMM16()
+#define CHECK_B_SET()
+#define CHECK_B_CLEAR()
+#define CHECK_MOD()
+#define CHECK_10f()
+#define CHECK_008()
+#define CHECK_00f()
+#define CHECK_0f0()
+#define CHECK_1f0()
+#define CHECK_RPL()
+#define CHECK_ST(d)
+#endif
+
+ssp1601_t *ssp = NULL;
static unsigned short *PC;
static int g_cycles;
-// debug
+
+#ifdef USE_DEBUGGER
static int running = 0;
static int last_iram = 0;
+#endif
// -----------------------------------------------------
// register i/o handlers
// 0-4, 13
static u32 read_unknown(void)
{
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown read @ %04x", GET_PPC_OFFS());
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
return 0;
}
static void write_unknown(u32 d)
{
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown write @ %04x", GET_PPC_OFFS());
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
}
// 4
static void write_ST(u32 d)
{
- if ((rST ^ d) & 7) {
- elprintf(EL_SVP, "ssp16: RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
-// running = 0;
- }
+ CHECK_ST(d);
rST = d;
}
// 5
static u32 read_STACK(void)
{
- //elprintf(EL_SVP, "pop %i @ %04x", rSTACK, GET_PPC_OFFS());
--rSTACK;
if ((short)rSTACK < 0) {
rSTACK = 5;
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
}
return ssp->stack[rSTACK];
}
static void write_STACK(u32 d)
{
if (rSTACK >= 6) {
- running = 0;
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
rSTACK = 0;
}
ssp->stack[rSTACK++] = d;
// 7
static u32 read_P(void)
{
- rP.v = (u32)rX * rY * 2;
+ int m1 = (signed short)rX;
+ int m2 = (signed short)rY;
+ rP.v = (m1 * m2 * 2);
return rP.h;
}
// -----------------------------------------------------
-static void iram_write(int addr, u32 d, int reg, int inc)
+static int get_inc(int mode)
{
- if ((addr&0xfc00) != 0x8000)
- elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
- elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
- ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
- ssp->pmac_write[reg] += inc<<16;
+ int inc = (mode >> 11) & 7;
+ if (inc != 0) {
+ if (inc != 7) inc--;
+ inc = 1 << inc; // 0 1 2 4 8 16 32 128
+ if (mode & 0x8000) inc = -inc; // decrement mode
+ }
+ return inc;
}
-int lil[32] = { 0, }, lilp = 0;
-
-static void debug_dump2file(const char *fname, void *mem, int len);
-
-#define overwite_write(dst, d) \
+#define overwrite_write(dst, d) \
{ \
if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
{
// this MUST be blind r or w
if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
- elprintf(EL_SVP|EL_ANOMALY, "FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
ssp->emu_status &= ~SSP_PMC_SET;
return 0;
elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
ssp->emu_status &= ~SSP_PMC_SET;
- if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
- elprintf(EL_SVP, "IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
-/*
- {
- int i;
- char buff[64];
- for (i = 0; i < 32; i++) {
- if (lil[i] == last_iram) break;
- if (lil[i] == 0) {
- lil[i] = last_iram;
- sprintf(buff, "iramrom_%04x.bin", last_iram);
- debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
- break;
- }
- }
- }
-*/
+ if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) {
+ elprintf(EL_SVP, "ssp IRAM copy from %06x to %04x", (ssp->RAM1[0]-1)<<1, (rPMC.v&0x7fff)<<1);
+#ifdef USE_DEBUGGER
last_iram = (ssp->RAM1[0]-1)<<1;
+#endif
}
return 0;
}
// just in case
if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
- elprintf(EL_SVP|EL_ANOMALY, "FIXME: PM%i (%c) with only addr set @ %04x",
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
reg, write ? 'w' : 'r', GET_PPC_OFFS());
ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
}
-// if (ssp->pmac_read[reg] != 0)
if (reg == 4 || (rST & 0x60))
{
#define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
unsigned short *dram = (unsigned short *)svp->dram;
if (write)
{
- /* TODO: 0c18 mode? */
- int mode = ssp->pmac_write[reg]&0xffff;
- int addr = ssp->pmac_write[reg]>>16;
- switch (mode) {
- case 0x0018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x", reg, CADDR, d);
- dram[addr] = d;
- break;
- case 0x0418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr)", reg, CADDR, d);
- overwite_write(dram[addr], d);
- break;
- case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc 1)", reg, CADDR, d);
- dram[addr] = d;
- ssp->pmac_write[reg] += 1<<16;
- break;
- case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
- case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
- case 0x4018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc)", reg, CADDR, d);
- dram[addr] = d;
- ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
- break;
- case 0x4418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr, cell inc)", reg, CADDR, d);
- overwite_write(dram[addr], d);
- ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
- break;
- default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
- reg, mode, CADDR, d, GET_PPC_OFFS()); break;
+ int mode = ssp->pmac_write[reg]>>16;
+ int addr = ssp->pmac_write[reg]&0xffff;
+ if ((mode & 0xb800) == 0xb800)
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
+ if ((mode & 0x43ff) == 0x0018) // DRAM
+ {
+ int inc = get_inc(mode);
+ elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
+ reg, CADDR, d, inc, (mode>>10)&1);
+ if (mode & 0x0400) {
+ overwrite_write(dram[addr], d);
+ } else dram[addr] = d;
+ ssp->pmac_write[reg] += inc;
+ }
+ else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
+ {
+ elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
+ reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
+ if (mode & 0x0400) {
+ overwrite_write(dram[addr], d);
+ } else dram[addr] = d;
+ ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
+ }
+ else if ((mode & 0x47ff) == 0x001c) // IRAM
+ {
+ int inc = get_inc(mode);
+ if ((addr&0xfc00) != 0x8000)
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
+ elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
+ ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
+ ssp->pmac_write[reg] += inc;
+ }
+ else
+ {
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
+ reg, mode, CADDR, d, GET_PPC_OFFS());
}
}
else
{
- int mode = ssp->pmac_read[reg]&0xffff;
- int addr = ssp->pmac_read[reg]>>16;
- if ((mode & 0xfff0) == 0x0800) { // ROM, inc 1, verified to be correct
+ int mode = ssp->pmac_read[reg]>>16;
+ int addr = ssp->pmac_read[reg]&0xffff;
+ if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
+ {
elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
- ssp->pmac_read[reg] += 1<<16;
+ ssp->pmac_read[reg] += 1;
d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
- goto ext_io_end;
}
-
- switch (mode) {
- case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", CADDR, dram[addr]);
- d = dram[addr]; // checked
- break;
- case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc 1)", reg, CADDR, dram[addr]);
- ssp->pmac_read[reg] += 1<<16;
- d = dram[addr];
- break;
- case 0x3018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 32)", CADDR, dram[addr]);
- ssp->pmac_read[reg] += 32<<16;
- d = dram[addr];
- break;
- case 0xa818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 16)", CADDR, dram[addr]);
- ssp->pmac_read[reg] -= 16<<16;
- d = dram[addr];
- break;
- case 0xb818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 128?)", CADDR, dram[addr]);
- ssp->pmac_read[reg] -= 128<<16;
- d = dram[addr];
- break;
- default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled read mode %04x, [%06x] @ %04x",
- reg, mode, CADDR, GET_PPC_OFFS());
- d = 0;
- break;
+ else if ((mode & 0x47ff) == 0x0018) // DRAM
+ {
+ int inc = get_inc(mode);
+ elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr]);
+ d = dram[addr];
+ ssp->pmac_read[reg] += inc;
+ }
+ else
+ {
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
+ reg, mode, CADDR, GET_PPC_OFFS());
+ d = 0;
}
}
-ext_io_end:
// PMC value corresponds to last PMR accessed (not sure).
rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
u32 d = pm_io(1, 0, 0);
if (d != (u32)-1) return d;
// can be removed?
- elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
return rPM1;
}
u32 r = pm_io(1, 1, d);
if (r != (u32)-1) return;
// can be removed?
- elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
rPM1 = d;
}
u32 d = pm_io(2, 0, 0);
if (d != (u32)-1) return d;
// can be removed?
- elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
return rPM2;
}
u32 r = pm_io(2, 1, d);
if (r != (u32)-1) return;
// can be removed?
- elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
rPM2 = d;
}
}
if (d != (u32)-1) return d;
// can be removed?
- elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
return rPM4;
}
u32 r = pm_io(4, 1, d);
if (r != (u32)-1) return;
// can be removed?
- elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
rPM4 = d;
}
// 14
static u32 read_PMC(void)
{
+ elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.l,
+ (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
- if (ssp->emu_status & SSP_PMC_SET)
- elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
+ //if (ssp->emu_status & SSP_PMC_SET)
+ // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
ssp->emu_status |= SSP_PMC_SET;
ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
- elprintf(EL_SVP, "PMC r m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
- return rPMC.l;
+ return ((rPMC.l << 4) & 0xfff0) | ((rPMC.l >> 4) & 0xf);
} else {
ssp->emu_status |= SSP_PMC_HAVE_ADDR;
- elprintf(EL_SVP, "PMC r a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
- return rPMC.h;
+ return rPMC.l;
}
}
static void write_PMC(u32 d)
{
if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
- if (ssp->emu_status & SSP_PMC_SET)
- elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
+ //if (ssp->emu_status & SSP_PMC_SET)
+ // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
ssp->emu_status |= SSP_PMC_SET;
ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
- rPMC.l = d;
- elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
+ rPMC.h = d;
+ elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.h, GET_PPC_OFFS());
} else {
ssp->emu_status |= SSP_PMC_HAVE_ADDR;
- rPMC.h = d;
- elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
+ rPMC.l = d;
+ elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.l, GET_PPC_OFFS());
}
}
// 15
static u32 read_AL(void)
{
- // TODO: figure out what's up with those blind reads..
- if (*(PC-1) == 0x000f) {
- elprintf(EL_SVP|EL_ANOMALY, "ssp dummy PM assign %08x, ST=%04x @ %04x", rPMC.v, rST, GET_PPC_OFFS());
- ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
- } else {
- //elprintf(EL_SVP, "ssp AL read, ST=%04x @ %04x", rST, GET_PPC_OFFS());
- }
+ if (*(PC-1) == 0x000f)
+ elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
+ ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
return rAL;
}
static void write_AL(u32 d)
{
- //elprintf(EL_SVP, "ssp AL write %04x, ST=%04x @ %04x", d, rST, GET_PPC_OFFS());
rAL = d;
}
// mod=1 (01), "+!"
// mod=3, "+"
case 0x08:
- case 0x18:
case 0x09:
- case 0x19:
- case 0x0a:
- case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
+ case 0x0a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
case 0x0b: ssp->RAM0[1] = d; return;
case 0x0c:
- case 0x1c:
case 0x0d:
- case 0x1d:
- case 0x0e:
- case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
+ case 0x0e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
case 0x0f: ssp->RAM1[1] = d; return;
// mod=2 (10), "-"
case 0x10:
case 0x11:
- case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
+ case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; CHECK_RPL(); return;
case 0x13: ssp->RAM0[2] = d; return;
case 0x14:
case 0x15:
- case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
+ case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; CHECK_RPL(); return;
case 0x17: ssp->RAM1[2] = d; return;
- // mod=3 (11)
+ // mod=3 (11), "+"
+ case 0x18:
+ case 0x19:
+ case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; CHECK_RPL(); return;
case 0x1b: ssp->RAM0[3] = d; return;
+ case 0x1c:
+ case 0x1d:
+ case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; CHECK_RPL(); return;
case 0x1f: ssp->RAM1[3] = d; return;
}
}
// -----------------------------------------------------
-void ssp1601_reset(ssp1601_t *l_ssp)
+#if defined(USE_DEBUGGER)
+static void debug_dump2file(const char *fname, void *mem, int len)
{
- ssp = l_ssp;
- ssp->emu_status = 0;
- ssp->gr[SSP_GR0].v = 0xffff0000;
- rPC = 0x400;
- rSTACK = 0; // ? using ascending stack
- rST = 0;
+ FILE *f = fopen(fname, "wb");
+ unsigned short *p = mem;
+ int i;
+ if (f) {
+ for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
+ fwrite(mem, 1, len, f);
+ fclose(f);
+ for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
+ printf("dumped to %s\n", fname);
+ }
+ else
+ printf("dump failed\n");
}
+#endif
-
+#ifdef USE_DEBUGGER
static void debug_dump(void)
{
printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
- printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
+ printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, rP.v);
printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
- printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
+ printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, rPMC.v);
printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
}
}
-static void debug_dump2file(const char *fname, void *mem, int len)
-{
- FILE *f = fopen(fname, "wb");
- unsigned short *p = mem;
- int i;
- if (f) {
- for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
- fwrite(mem, 1, len, f);
- fclose(f);
- for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
- printf("dumped to %s\n", fname);
- }
- else
- printf("dump failed\n");
-}
-
static int bpts[10] = { 0, };
static void debug(unsigned int pc, unsigned int op)
}
}
}
+#endif // USE_DEBUGGER
+
+
+void ssp1601_reset(ssp1601_t *l_ssp)
+{
+ ssp = l_ssp;
+ ssp->emu_status = 0;
+ ssp->gr[SSP_GR0].v = 0xffff0000;
+ rPC = 0x400;
+ rSTACK = 0; // ? using ascending stack
+ rST = 0;
+}
+
void ssp1601_run(int cycles)
{
SET_PC(rPC);
- g_cycles = cycles;
-//if (Pico.m.frame_count == 480) running = 0;
+ g_cycles = cycles;
while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
{
u32 tmpv;
op = *PC++;
+#ifdef USE_DEBUGGER
debug(GET_PC()-1, op);
+#endif
switch (op >> 9)
{
// ld d, s
case 0x00:
+ CHECK_B_SET();
if (op == 0) break; // nop
if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
- // not sure. MAME claims that only hi word is transfered.
read_P(); // update P
- ssp->gr[SSP_A].v = ssp->gr[SSP_P].v;
+ rA32 = rP.v;
}
else
{
case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
// ldi d, imm
- case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+ case 0x04: CHECK_10f(); tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles--; break;
// ld d, ((ri))
- case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+ case 0x05: CHECK_MOD(); tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles -= 2; break;
// ldi (ri), imm
- case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
+ case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); g_cycles--; break;
// ld adr, a
case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
// ld d, ri
- case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+ case 0x09: CHECK_MOD(); tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
// ld ri, s
- case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
+ case 0x0a: CHECK_MOD(); rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
// ldi ri, simm
case 0x0c:
// call cond, addr
case 0x24: {
int cond = 0;
+ CHECK_00f();
COND_CHECK
- if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
+ if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); SET_PC(new_PC); }
else PC++;
+ g_cycles--; // always 2 cycles
break;
}
// ld d, (a)
- case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+ case 0x25:
+ CHECK_10f();
+ tmpv = ((unsigned short *)svp->iram_rom)[rA];
+ REG_WRITE((op & 0xf0) >> 4, tmpv);
+ g_cycles -= 2; // 3 cycles total
+ break;
// bra cond, addr
case 0x26: {
int cond = 0;
+ CHECK_00f();
COND_CHECK
- if (cond) { int new_PC = *PC++; write_PC(new_PC); }
+ if (cond) { int new_PC = *PC++; SET_PC(new_PC); }
else PC++;
+ g_cycles--;
break;
}
// mod cond, op
case 0x48: {
int cond = 0;
+ CHECK_008();
COND_CHECK
if (cond) {
switch (op & 7) {
case 3: rA32 <<= 1; break; // shl
case 6: rA32 = -(signed int)rA32; break; // neg
case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
- default: elprintf(EL_SVP, "ssp16: FIXME unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
+ default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
+ op&7, GET_PPC_OFFS());
}
- UPD_ACC_ZN // ?
+ UPD_ACC_ZN
}
break;
}
-#if 1
// mpys?
case 0x1b:
- // very uncertain about this one. What about b?
- if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
+ CHECK_B_CLEAR();
read_P(); // update P
- ssp->gr[SSP_A].v -= ssp->gr[SSP_P].v; // maybe only upper word?
-// UPD_ACC_ZN // I've seen code checking flags after this
- rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
- rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
+ rA32 -= rP.v;
+ UPD_ACC_ZN
+ rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
+ rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
break;
-#endif
+
// mpya (rj), (ri), b
case 0x4b:
- // dunno if this is correct. What about b?
- if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
+ CHECK_B_CLEAR();
read_P(); // update P
- ssp->gr[SSP_A].v += ssp->gr[SSP_P].v; // maybe only upper word?
- UPD_ACC_ZN // ?
- rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
- rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
+ rA32 += rP.v;
+ UPD_ACC_ZN
+ rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
+ rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
break;
// mld (rj), (ri), b
case 0x5b:
- // dunno if this is correct. What about b?
- if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
- ssp->gr[SSP_A].v = 0; // maybe only upper word?
- // UPD_t_LZVN // ?
- rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
- rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
+ CHECK_B_CLEAR();
+ rA32 = 0;
+ rST &= 0x0fff;
+ rST |= SSP_FLAG_Z;
+ rX = ptr1_read_(op&3, 0, (op<<1)&0x18);
+ rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18);
break;
// OP a, s
- case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
- case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
- case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
- case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
- case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
- case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
+ case 0x10: CHECK_1f0(); OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
+ case 0x30: CHECK_1f0(); OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
+ case 0x40: CHECK_1f0(); OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
+ case 0x50: CHECK_1f0(); OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
+ case 0x60: CHECK_1f0(); OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
+ case 0x70: CHECK_1f0(); OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
// OP a, (ri)
- case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
- case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
- case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
- case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
- case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
- case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
+ case 0x11: CHECK_0f0(); tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
+ case 0x31: CHECK_0f0(); tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
+ case 0x41: CHECK_0f0(); tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
+ case 0x51: CHECK_0f0(); tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
+ case 0x61: CHECK_0f0(); tmpv = ptr1_read(op); OP_ORA (tmpv); break;
+ case 0x71: CHECK_0f0(); tmpv = ptr1_read(op); OP_EORA(tmpv); break;
// OP a, adr
case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
// OP a, imm
- case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
- case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
- case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
- case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
- case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
- case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
+ case 0x14: CHECK_IMM16(); tmpv = *PC++; OP_SUBA(tmpv); g_cycles--; break;
+ case 0x34: CHECK_IMM16(); tmpv = *PC++; OP_CMPA(tmpv); g_cycles--; break;
+ case 0x44: CHECK_IMM16(); tmpv = *PC++; OP_ADDA(tmpv); g_cycles--; break;
+ case 0x54: CHECK_IMM16(); tmpv = *PC++; OP_ANDA(tmpv); g_cycles--; break;
+ case 0x64: CHECK_IMM16(); tmpv = *PC++; OP_ORA (tmpv); g_cycles--; break;
+ case 0x74: CHECK_IMM16(); tmpv = *PC++; OP_EORA(tmpv); g_cycles--; break;
// OP a, ((ri))
- case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
- case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
- case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
- case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
- case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
- case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
+ case 0x15: CHECK_MOD(); tmpv = ptr2_read(op); OP_SUBA(tmpv); g_cycles -= 2; break;
+ case 0x35: CHECK_MOD(); tmpv = ptr2_read(op); OP_CMPA(tmpv); g_cycles -= 2; break;
+ case 0x45: CHECK_MOD(); tmpv = ptr2_read(op); OP_ADDA(tmpv); g_cycles -= 2; break;
+ case 0x55: CHECK_MOD(); tmpv = ptr2_read(op); OP_ANDA(tmpv); g_cycles -= 2; break;
+ case 0x65: CHECK_MOD(); tmpv = ptr2_read(op); OP_ORA (tmpv); g_cycles -= 2; break;
+ case 0x75: CHECK_MOD(); tmpv = ptr2_read(op); OP_EORA(tmpv); g_cycles -= 2; break;
// OP a, ri
- case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
- case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
- case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
- case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
- case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
- case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
+ case 0x19: CHECK_MOD(); tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
+ case 0x39: CHECK_MOD(); tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
+ case 0x49: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
+ case 0x59: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
+ case 0x69: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
+ case 0x79: CHECK_MOD(); tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
// OP simm
- case 0x1c: OP_SUBA(op & 0xff); break;
- case 0x3c: OP_CMPA(op & 0xff); break;
- case 0x4c: OP_ADDA(op & 0xff); break;
- // MAME code only does LSB of top word, but this looks wrong to me.
- case 0x5c: OP_ANDA(op & 0xff); break;
- case 0x6c: OP_ORA (op & 0xff); break;
- case 0x7c: OP_EORA(op & 0xff); break;
+ case 0x1c: CHECK_B_SET(); OP_SUBA(op & 0xff); break;
+ case 0x3c: CHECK_B_SET(); OP_CMPA(op & 0xff); break;
+ case 0x4c: CHECK_B_SET(); OP_ADDA(op & 0xff); break;
+ case 0x5c: CHECK_B_SET(); OP_ANDA(op & 0xff); break;
+ case 0x6c: CHECK_B_SET(); OP_ORA (op & 0xff); break;
+ case 0x7c: CHECK_B_SET(); OP_EORA(op & 0xff); break;
default:
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
break;
}
g_cycles--;
}
- read_P(); // update P
rPC = GET_PC();
-
- if (ssp->gr[SSP_GR0].v != 0xffff0000)
- elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
+ read_P(); // update P
}
notaz.gp2x.de / picodrive.git / blobdiff